ADSP-21262SKSTZ200 Analog Devices Inc, ADSP-21262SKSTZ200 Datasheet - Page 34

• Manufacturer Part Number: ADSP-21262SKSTZ200
• Description: IC DSP CONTROLLER 32BIT 144-LQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21262SKSTZ200

• Interface: DAI, SPI
• Clock Rate: 200MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• No. Of Bits: 32 / 40
• Frequency: 200MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: Host Port, Serial
• Supply Voltage Range: 1.14V To 1.26V
• Operating Temperature Range: 0°C To +70°C
• Package: 144LQFP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 200 MHz
• Ram Size: 256 KB
• Device Million Instructions Per Second: 200 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP21262SKSTZ200; ADSP21262SKSTZ200

ADSP-21262
SPI Protocol—Master
Table 29. SPI Protocol—Master
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
SSPIDM
HSPIDM
SPICLKM
SPICHM
SPICLM
DDSPIDM
HDSPIDM
SDSCIM
HDSM
SPITDM
CPHASE = 1
CPHASE = 0
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
SPICLK
(CP = 0)
SPICLK
(CP = 1)
(INPUT)
(INPUT)
FLG3-0
MISO
MOSI
MOSI
MISO
t
S S P I D M
Data Input Valid to SPICLK Edge (Data Input Setup Time)
SPICLK Last Sampling Edge to Data Input Not Valid
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
FLAG3–0 OUT (SPI Device Select) Low to First SPICLK Edge
Last SPICLK Edge to FLAG3–0 OUT High
Sequential Transfer Delay
t
S D S C I M
VALID
MSB
t
t
MSB
S P I C H M
S P IC LM
VALID
MSB
t
H S P ID M
t
t
D D S P I D M
t
t
S S P ID M
MSB
S P IC LM
S P I C H M
t
D D S P I D M
Rev. B | Page 34 of 48 | August 2005
t
Figure 25. SPI Protocol—Master
H S P I D M
t
H D S P I D M
t
t
S S P I D M
HDSPIDM
t
VALID
S P IC LK M
LSB
LSB
VALID
LSB
Min
5
2
8 × t
4 × t
4 × t
10
4 × t
4 × t
4 × t
t
H D S M
LSB
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
t
– 2
– 2
– 2
– 1
– 1
H S P I D M
t
S P I T D M
Max
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns