ADSP-21262SKSTZ200 Analog Devices Inc, ADSP-21262SKSTZ200 Datasheet - Page 32

• Manufacturer Part Number: ADSP-21262SKSTZ200
• Description: IC DSP CONTROLLER 32BIT 144-LQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21262SKSTZ200

• Interface: DAI, SPI
• Clock Rate: 200MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• No. Of Bits: 32 / 40
• Frequency: 200MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: Host Port, Serial
• Supply Voltage Range: 1.14V To 1.26V
• Operating Temperature Range: 0°C To +70°C
• Package: 144LQFP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 200 MHz
• Ram Size: 256 KB
• Device Million Instructions Per Second: 200 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP21262SKSTZ200; ADSP21262SKSTZ200

ADSP-21262
Input Data Port (IDP)
The timing requirements for the IDP are given in
Figure
DAI_P20–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DAI_P20–1 pins.
Table 27. Input Data Port (IDP)
1
Parameter
Timing Requirements
t
t
t
t
t
t
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via the precision clock generators (PCG) or SPORTs. PCG input can be either
SISFS
SIHFS
SISD
SIHD
IDPCLKW
IDPCLK
CLKIN or any of the DAI pins.
23. IDP Signals (SCLK, FS, SDATA) are routed to the
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SData Setup Before SCLK Rising Edge
SData Hold After SCLK Rising Edge
Clock Width
Clock Period
DAI_P20
DAI_P20
DAI_P20
(SDATA)
(SCLK)
(FS)
–
–
–
1
1
1
1
Table 27
1
Rev. B | Page 32 of 48 | August 2005
1
Figure 23. Input Data Port (IDP)
1
and
t
IDPCLKW
t
SISFS
t
SISD
SAMPLE EDGE
Min
2.5
2.5
2.5
2.5
7
20
t
t
SIHFS
SIHD
Max
Unit
ns
ns
ns
ns
ns
ns