ADSP-21262SKSTZ200 Analog Devices Inc, ADSP-21262SKSTZ200 Datasheet - Page 30

• Manufacturer Part Number: ADSP-21262SKSTZ200
• Description: IC DSP CONTROLLER 32BIT 144-LQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21262SKSTZ200

• Interface: DAI, SPI
• Clock Rate: 200MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• No. Of Bits: 32 / 40
• Frequency: 200MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: Host Port, Serial
• Supply Voltage Range: 1.14V To 1.26V
• Operating Temperature Range: 0°C To +70°C
• Package: 144LQFP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 200 MHz
• Ram Size: 256 KB
• Device Million Instructions Per Second: 200 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP21262SKSTZ200; ADSP21262SKSTZ200

ADSP-21262
Table 25. Serial Ports—Enable and Three-State
1
Table 26. Serial Ports—External Late Frame Sync
1
1
Parameter
Switching Characteristics
t
t
t
Parameter
Switching Characteristics
t
t
Referenced to drive edge.
The t
This figure reflects changes made to support left-justified sample pair mode.
DDTEN
DDTTE
DDTIN
DDTLFSE
DDTENFS
DDTLFSE
and t
DDTENFS
Data Enable from External Transmit SCLK
Data Disable from External Transmit SCLK
Data Enable from Internal Transmit SCLK
Data Delay from Late External Transmit FS or External Receive FS
with MCE = 1, MFD = 0
Data Enable for MCE = 1, MFD = 0
parameters apply to left-justified sample pair mode as well as DSP serial mode, and MCE = 1, MFD = 0.
(DATA CHANNEL A/B)
(DATA CHANNEL A/B)
NOTE: SERIAL PORT SIGNALS (SCLK, FS,
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P[20:1] PINS.
DAI_P20-1
DAI_P20-1
DAI_P20-1
DAI_P20-1
DAI_P20-1
DAI_P201
(SCLK)
(SCLK)
(FS)
(FS)
1
DRIVE
DRIVE
t
DDTLFSE
t
DDTLFSE
1
Figure 21. External Late Frame Sync
Rev. B | Page 30 of 48 | August 2005
t
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
t
SFSE/I
SFSE/I
t
LATE EXTERNAL TRANSMIT FS
DDTENFS
t
DDTENFS
1
1
1
SAMPLE
SAMPLE
1ST BIT
DATA CHANNEL
1ST BIT
t
HDTE/I
t
HDTE/I
DRIVE
DRIVE
A/B) ARE ROUTED TO THE DAI_P[20:1] PINS
t
t
HFSE/I
HFSE/I
1
Min
2
–1
Min
0.5
t
DDTE/I
t
DDTE/I
2ND BIT
2ND BIT
Max
7
Max
7
Unit
ns
ns
ns
Unit
ns
ns