ADSP-BF532SBSTZ400 Analog Devices Inc, ADSP-BF532SBSTZ400 Datasheet - Page 7

• Manufacturer Part Number: ADSP-BF532SBSTZ400
• Description: IC DSP CTLR 16BIT 400MHZ 176LQFP
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF532SBSTZ400

• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 84kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP
• No. Of Bits: 16 Bit
• Frequency: 400MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: PPI, SPI, UART
• No. Of I/o's: 16
• Supply Voltage Range: 0.8V To 1.45V, 1.75V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Silicon Anomaly List
6.
05000158 - Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications):
DESCRIPTION:
After a DMA or core MMR DTEST register access has occurred to the L1 instruction memory, a data cache fill to the corresponding port
may get corrupted data. This situation can only occur if stalls are introduced because the core is accessing the same data memory bank as
the data cache fill.
This data cache fill can occur many cycles after the L1 Instruction memory DMA or MMR access. One example of the failure is when a
program that enables data cache is booted. The Instruction DMA that occurred during the boot may prime the processor to be
susceptible to data corruption in a data cache fill that occurs sometime during the main program's execution.
For Port A, data locations 0xFF80xxxx and instruction locations 0xFFA00000 -0xFFA07FFF (where applicable) are subject to the failure. For
Port B, data locations 0xFF90xxxx and instruction locations 0xFFA08000 - 0xFFA0FFFF (where applicable) are subject to the failure.
The problem will also occur if the last DMA transaction was to the L1 instruction memory while a low priority data cache fill is ongoing.
WORKAROUND:
The best workaround for this issue is to set bit 9 of any DCPLB Data register that you use. This bit is shown as a reserved bit in the
Hardware Reference Manual, but the documentation is being updated to describe the functionality of this bit.
A second workaround would be to perform a software core reset at the beginning of the program:
If the program will be performing both data caching and L1 Instruction Memory DMA, perform a Data DMA to the data SRAM which
shares a data port with the Instruction SRAM after performing an Instruction DMA. Do not perform any access that would cause data
caching or victimization from the time the Instruction DMA begins until after the Data DMA has completed. Also, an MMR DTEST access to
the corresponding data bank could also clear out the problem if the original problem was caused by the Instruction Memory DMA.
If the program will access the L1 Instruction Memory through the core MMR DTEST register, follow this access with a core MMR DTEST
register access to the corresponding Data Bank.
If the processor is either not DMAing to instruction memory or not using data cache, you will not encounter this problem.
The VisualDSP++ runtime libraries cache support functions contain a workaround for this anomaly where necessary.
APPLIES TO REVISION(S):
0.3, 0.4
P0.H = HI(SYSCR);
P0.L = LO(SYSCR);
R0.L = W[P0];
CC = BITTST(R0,4);
IF CC JUMP _No_Boot_Set;
BITSET(R0,4);
W[P0] = R0;
SSYNC;
RAISE 1;
_No_Boot_Set:
BITCLR(R0,4);
W[P0] = R0;
// Check System Reset Configuration Register
// Check NO BOOT ON SOFTWARE RESET Bit
// Set NO BOOT ON SOFTWARE RESET Bit
// Ensure write completes before executing RAISE
// Reset SYSCR to original value
NR003532D | Page 7 of 45 | July 2008
ADSP-BF531/BF532/BF533