ADSP-BF532SBSTZ400 Analog Devices Inc, ADSP-BF532SBSTZ400 Datasheet - Page 31

• Manufacturer Part Number: ADSP-BF532SBSTZ400
• Description: IC DSP CTLR 16BIT 400MHZ 176LQFP
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF532SBSTZ400

• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 84kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP
• No. Of Bits: 16 Bit
• Frequency: 400MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: PPI, SPI, UART
• No. Of I/o's: 16
• Supply Voltage Range: 0.8V To 1.45V, 1.75V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Silicon Anomaly List
54.
55.
DESCRIPTION:
When the Core Clock is not at least twice as fast as the the System Clock, 32-bit or wider writes to SDRAM memory may be lost. Note that
since cache victims are effectively 256 bit wide writes, cache victimization will also trigger this anomaly.
WORKAROUND:
Either:
1) Make sure that the Core Clock (CCLK) is at least twice as fast as the System Clock (SCLK)
or
2) Make sure all external memory writes are 16 bits wide or less:
If using data cache, the Write Through policy should be used since there is no cache victimization in this mode.
APPLIES TO REVISION(S):
0.3, 0.4, 0.5
DESCRIPTION:
The PPI timing diagrams in the processor data sheet only apply to PPI modes where the PPI_DELAY register is set to zero.
WORKAROUND:
For non-zero values of the PPI_DELAY register, the following information applies:
In the data sheet, when POLC = 0, the frame sync is sampled on the falling edge of the PPI clock and the corresponding setup time is
shown relative to this edge. When the PPI_DELAY register is a non-zero value, the frame sync setup time increases by one half the period
of the PPI clock. The delay starts counting at the point on the existing diagrams where data is shown to be sampled.
In the data sheet, when POLC = 1, the frame sync is sampled on the rising edge of the PPI clock and the corresponding setup time is
shown relative to this edge. When the PPI_DELAY register is a non-zero value, the frame sync setup time increases by one half the period
of the PPI clock. The delay starts counting at the point on the existing diagrams where data is shown to be sampled.
APPLIES TO REVISION(S):
0.3, 0.4, 0.5, 0.6
05000273 - Writes to Synchronous SDRAM Memory May Be Lost:
05000276 - Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY:
W[P2] = R0;
B[P2] = R0;
// 16-bit write
//
8-bit write
NR003532D | Page 31 of 45 | July 2008
ADSP-BF531/BF532/BF533