ADSP-BF532SBSTZ400 Analog Devices Inc, ADSP-BF532SBSTZ400 Datasheet - Page 34

• Manufacturer Part Number: ADSP-BF532SBSTZ400
• Description: IC DSP CTLR 16BIT 400MHZ 176LQFP
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF532SBSTZ400

• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 84kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP
• No. Of Bits: 16 Bit
• Frequency: 400MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: PPI, SPI, UART
• No. Of I/o's: 16
• Supply Voltage Range: 0.8V To 1.45V, 1.75V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-BF531/BF532/BF533
60.
DESCRIPTION:
Consider the following sequence:
1) System MMR write is stalled.
2) Interrupt occurs while the System MMR write is stalled (thus killing the write).
3) Interrupt Service Routine performs an "ssync;" instruction.
In order for this anomaly to happen, the interrupt must kill the write in one particular stage of the execution pipeline. In this case, the
anomaly will cause the MMR logic to think that the killed System MMR access is still valid. The "ssync;" will therefore stall the processor
indefinitely or until it is interrupted itself by a higher priority interrupt or event.
Similarly, if the System MMR write is killed by an instruction itself, such as a conditional branch, the infinite stall can happen if the store
buffer is full and emptying out to slow external memory.
NOTE: if a user tries to halt the processor in the ISR via the debugging tools, the infinite stall will also lock out the Emulation event.
WORKAROUND:
The workaround is to reset the MMR logic with another killed System MMR access that has no other side effects on the application. For
instance, read from the CHIPID register. The following code snippet, executed at the beginning of each ISR, will work around this anomaly:
In the case of MMR writes being killed by the conditional branches, it is sufficient to insert 2 NOPs or any other non-MMR instructions in
the location immediately after the conditional branch.
NOTE: in order to prevent lock-ups during debugging sessions, always set breakpoint after the above code snippet if you need to halt the
processor in the ISR.
APPLIES TO REVISION(S):
0.3, 0.4, 0.5
05000283 - System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage:
cc = r0 == r0;
if cc jump skip;
W[p0] = r1.l;
skip: ...
cc = r0 == r0;
p0.h = 0xffc0;
p0.l = 0x0014;
if cc jump skip; // always skip MMR access, but MMR access is fetched and killed
r0 = [p0];
skip: ...
// always true
// System MMR access is fetched and killed
// always true
// System MMR space CHIPID
// bogus System MMR read to work around the anomaly
// continue with ISR
NR003532D | Page 34 of 45 | July 2008
Silicon Anomaly List