ADSP-BF532SBSTZ400 Analog Devices Inc, ADSP-BF532SBSTZ400 Datasheet - Page 45

• Manufacturer Part Number: ADSP-BF532SBSTZ400
• Description: IC DSP CTLR 16BIT 400MHZ 176LQFP
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF532SBSTZ400

• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 84kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP
• No. Of Bits: 16 Bit
• Frequency: 400MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: PPI, SPI, UART
• No. Of I/o's: 16
• Supply Voltage Range: 0.8V To 1.45V, 1.75V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Silicon Anomaly List
79.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
DESCRIPTION:
When an external FIFO device is connected to an asynchronous memory bank, memory accesses can be performed by the processor
speculatively, causing improper operations because the FIFO will provide data to the Blackfin, and the data will be dropped whenever the
fetch is made speculatively or if the speculative access is canceled. "Speculative" fetches are reads that are started and killed in the
pipeline prior to completion. They are caused by either a change of flow (including an interrupt or exception) or when performing an
access in the shadow of a branch. This behavior is described in the Blackfin Programmer's Reference.
Another case that can occur is when the access is performed as part of a hardware loop, where a change of flow occurs from an exception.
Since exceptions can't be disabled, the following example shows how an exception can cause a speculative fetch, even with interrupts
disabled:
In this example, the read inside the hardware loop is made to a FIFO with interrupts disabled. When the write inside the loop generates a
data CPLB exception, the read inside the loop will be done speculatively.
WORKAROUND:
First, if the access is being performed with a core read, turn off interrupts prior to doing the core read. The read phase of the pipeline must
then be protected from seeing the read instruction before interrupts are turned off:
To protect against an exception causing the same undesired behavior, the read must be separated from the change of flow:
The loop could also be constructed to place the NOP padding at the end:
Both of these sequences prevent the change of flow from allowing the read to execute speculatively. The 2 inserted NOPs provide
enough separation in the pipeline to prevent a speculative access. These NOPs can be any two instructions.
Reads performed using a DMA transfer do not need to be protected from speculative accesses.
APPLIES TO REVISION(S):
0.3, 0.4, 0.5, 0.6
05000416 - Speculative Fetches Can Cause Undesired External FIFO Operations:
CLI R3;
LSETUP( loop_s, loop_e) LC0 = P2;
STI R3;
RTS;
CLI R0;
NOP; NOP; NOP;
R1 = [P0];
STI R0;
CLI R3;
LSETUP( loop_s, loop_e) LC0 = P2;
STI R3;
RTS;
LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
loop_s: R0 = W[P0];
loop_e: W[P1++] = R0;
loop_s: NOP;
loop_e: W[P1++] = R0;
.Lword_loop_s: R0 = W[P0];
.Lword_loop_e: NOP;
NOP;
R0 = W[P0];
/* Can Be Any 3 Instructions */
W[P1++] = R0;
NOP;
NR003532D | Page 45 of 45 | July 2008
/* 2 NOPs to Pad Read */
a
/* Disable Interrupts */
/* 2 NOPs to Pad Read */
/* Enable Interrupts */
/* Disable Interrupts */
/* Read from a FIFO Device
/* Write that Generates a Data CPLB Page Miss */
/* Enable Interrupts */
ADSP-BF531/BF532/BF533
*/
w w w . a n a l o g . c o m