ADSP-BF532SBSTZ400 Analog Devices Inc, ADSP-BF532SBSTZ400 Datasheet - Page 14

• Manufacturer Part Number: ADSP-BF532SBSTZ400
• Description: IC DSP CTLR 16BIT 400MHZ 176LQFP
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF532SBSTZ400

• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 84kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP
• No. Of Bits: 16 Bit
• Frequency: 400MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: PPI, SPI, UART
• No. Of I/o's: 16
• Supply Voltage Range: 0.8V To 1.45V, 1.75V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-BF531/BF532/BF533
23.
24.
DESCRIPTION:
The VSTAT status bit in the PLL_STAT register does not function. Relying on its value to determine whether the internal voltage regulator
has settled is not recommended.
WORKAROUND:
When changing the voltage via the internal voltage regulator, allow at least 40usec for the voltage change to take place. After 40usec, the
new value will be set, regardless of the state of the VSTAT bit.
APPLIES TO REVISION(S):
0.3, 0.4, 0.5, 0.6
DESCRIPTION:
The following instructions can sometimes operate incorrectly when the preceding instruction is creating the operand for the instruction.
The affected instructions are:
An example is shown for the Signbits instruction:
WORKAROUND:
There are two workarounds that will avoid the problem:
1) Precede signbits instructions with a nop:
2) Make sure the operand register for the signbits is not dependent on the previous instruction:
The VisualDSP++ Blackfin compiler includes a workaround for this hardware anomaly. The compiler will automatically enable the
workaround for the appropriate silicon revisions and part numbers, or the workaround can be enabled manually by specifying the
compiler flag '-workaround dreg-comp-latency'. The VisualDSP++ run-time libraries also avoid the anomaly conditions when necessary.
When enabled the compiler should insert a NOP instruction between two instructions where the first instruction assigns a value to a
DREG, and the second instruction uses the DREG as a parameter to a SIGNBITS, EXTRACT, DEPOSIT or EXPADJ instruction.
The compiler also defines the macros __WORKAROUND_DREG_COMP_LATENCY and __WORKAROUNDS_ENABLED at the source,
assembly and link build stages when this workaround is enabled.
APPLIES TO REVISION(S):
0.3
05000208 - VSTAT Status Bit in PLL_STAT Register Is Not Functional:
05000209 - Speed Path in Computational Unit Affects Certain Instructions:
EXTRACT (x)
DEPOSIT (x)
SIGNBITS
EXPADJ
r0 = ashift r2 by r3.l;
r1.l = signbits r0;
r0 = ashift r2 by r3.l;
nop;
r1.l = signbits r0;
r0 = ashift r2 by r3.l;
// ** another useful instruction that is not updating r0 **;
r1.l = signbits r0;
NR003532D | Page 14 of 45 | July 2008
Silicon Anomaly List