ADMCF340BST Analog Devices Inc, ADMCF340BST Datasheet - Page 26

• Manufacturer Part Number: ADMCF340BST
• Manufacturer: Analog Devices Inc

Specifications of ADMCF340BST

• Device Core Size: 16b
• Format: Fixed Point
• Clock Freq (max): 20MHz
• Mips: 20
• Device Input Clock Speed: 20MHz
• Ram Size: 1KB
• Program Memory Size: 12KB
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.44V
• Operating Supply Voltage (max): 2.55V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

ADMC(F)340
With SPORT1 configured in UART mode, the SPORT0 serial
clock (SCLK0) is externally available through the SCLK1/
SCLK0 pin. The SPORT1 data transmit (DT1) is externally
available through the FL1/DT1 pin.
SPORT0 Configuration
SPORT0 can be configured in SPORT, UART, and SPI modes.
SPORT0 can be configured for UART mode. In this mode,
the DR0 and RFS0 signals of the internal serial port are
connected together.
Figure 18. SPORT0 and SPORT1 Internal Multiplexing (Simplified Diagram)
SPORT0 SPORT MODE/UART MODE
DSP
CORE
SPORT1
DSP
CORE
SPORT0
ADMC(F)340
MODECTRL REGISTER (15)
SCLK1
SCLK0
RFS1
RFS0
TFS1
TFS0
DR1
DR0
DT1
DT0
FL1
SPORT1 BOOT MODE/UART MODE
MODECTRL REGISTER (04)
SPORT0 SPI INTERFACE CONTROL
MODECTRL REGISTER (14..13..12)
–26–
SPORT0 can be configured to operate as a master SPI interface. The
SPI mode is set through Bit 14 of the MODECTRL Register. When
SPORT0 is configured as an SPI interface, the SPORT I/O pins
assume the configuration shown in Table XI (ADMCF340 only).
The Slave Select pin automatically generates the select signal at
each word transfer (ADMCF340 only). This pin can also be used
as a general-purpose I/O during the SPI transfer without affecting
the SPORT operations (ADMCF340 only).
The SPI clock polarity and phase are configurable through Bits
13 and 12 of the MODECTRL Register (ADMCF340 only). The
SPI transfer using clock phase is shown in Figure 19 and
Figure 20 (ADMCF340 only).
CONTROL
BLOCK
SPI
DT1/FL1
DR1
SCLK1/SCLK0
DT0
DR0
TFS0
RFS0
REV. A