ADMCF340BST Analog Devices Inc, ADMCF340BST Datasheet - Page 10

• Manufacturer Part Number: ADMCF340BST
• Manufacturer: Analog Devices Inc

Specifications of ADMCF340BST

• Device Core Size: 16b
• Format: Fixed Point
• Clock Freq (max): 20MHz
• Mips: 20
• Device Input Clock Speed: 20MHz
• Ram Size: 1KB
• Program Memory Size: 12KB
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.44V
• Operating Supply Voltage (max): 2.55V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

ADMC(F)340
The ADMC(F)340 is available in a 64-lead LQFP package.
PIN FUNCTION DESCRIPTION
Pin Group
Name
PWMPOL
PWMSR
RESET
SPORT1
SPORT0
CLKOUT
CLKIN, XTAL
PORTA0–PORTA8
PORTB0–PORTB15 16
AUX0–AUX1
AH-CL
PWMTRIP
V1 to V3
I
VAUX0-VAUX7
ICONST
DV
AV
GND
NOTES
1
2
Multiplexed pins, individually selectable through PORTA_SELECT and
SCLK1/SCLK0 multiplexed signals, selectable through MODECTRL
SENSE1
PORTA_DATA Registers.
Register Bit 4.
• SPORT0 has one pin, SCLK0, shared with SPORT1.
• SPORT0 can be configured as a SPI Port (master mode only).
• SPORT0 has a multichannel interface to selectively receive
• SPORT1 is the default port for program/data memory boot
DD
DD
During a boot phase (SPORT1 Boot Mode enabled by a bit
in the MODECTRL Register), the serial clock of SPORT1 is
externally available. The serial clock of SPORT0 is externally
available when the SPORT1 is configured in UART Mode.
Refer to Table XI for more information. The clock phase and
polarity are programmable through the MODECTRL Register.
Refer to Table XI for pin configuration.
and transmit a 24-word or 32-word time division multiplexed
serial bit stream.
loading and for the development tools interface. The DT1/FL1
pin can be configured as the SROM/E
to I
1
1
1
SENSE3
1
1
No. of Input/
Pins
1
1
1
2
5
1
2
9
2
6
1
3
3
7
1
3
3
3
Table I. Pin List
1
Output Function
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I
I
I
I
O
I
I
I
PWM Polarity
PWM Switched
Reluctance Mode
Processor Reset Input
Serial Port 1 Pins
(DT1/FL1, DR1)
Serial Port 0 Pins
(DT0, DR0, RFS0,
TFS0, SCLK1/
SCLK0
Processor Clock
Output
External Clock or
Quartz Crystal
Connection Point
Digital I/O Port Pins
Digital I/O Port Pins
Auxiliary PWM
Outputs
PWM Outputs
PWM Trip Signal
I
Analog Inputs
Auxiliary Analog Inputs
ADC Constant
Current Source
Power Supply
Power Supply
Ground
SENSE
2
PROM reset signal.
Inputs
2
)
–10–
INTERRUPT OVERVIEW
The ADMC(F)340 can respond to 34 different interrupt sources
with minimal overhead, seven of which are internal DSP core
interrupts and 27 of which are from the motor control peripherals.
The seven DSP core interrupts are SPORT1 receive (or IRQ0)
and transmit (or IRQ1), SPORT0 receive and transmit, the
internal timer, and two software interrupts. The motor control
peripheral interrupts are the 25 programmable I/Os and two from
the PWM (PWMSYNC pulse and PWMTRIP). All motor control
interrupts are multiplexed into the DSP core through the periph-
eral IRQ2 interrupt. The interrupts are internally prioritized and
individually maskable. A detailed description of the entire interrupt
system of the ADMC(F)340 is presented in the Interrupt
Control section, which follows the detailed descriptions of each
peripheral block.
MEMORY MAP
The ADMC(F)340 has two distinct memory types: program
and data. In general, program memory contains user code and
coefficients, while the data memory is used to store variables and
data during program execution. Three kinds of program memory are
provided on the ADMC(F)340: RAM, ROM, and FLASH. The
motor control peripherals are memory mapped into a region of the
data memory space starting at 0x2000. The complete program and
data memory maps are given in Tables II and III, respectively.
Address Range
0x0000–0x002F
0x0030–0x01FF
0x0200–0x07FF
0x0800–0x17FF
0x1800–0x1FFF
0x2000–0x20FF
0x2100–0x21FF
0x2200–0x2FFF
0x3000–0x3FFF
Address Range
0x0000–0x1FFF
0x2000–0x20FF
0x2100–0x37FF
0x3800–0x39FF
0x3A00–0x3BFF
0x3C00–0x3FFF
Table II. Program Memory Map
Table III. Data Memory Map
Memory
Type
RAM
RAM
ROM
FLASH
FLASH
FLASH
Memory
Type
RAM
RAM
Function
Internal Vector Table
User Program Memory
Reserved
Reserved Program Memory
Reserved
User Program Memory
Sector 0
User Program Memory
Sector 1
User Program Memory
Sector 2
Reserved
Function
Reserved
Memory Mapped Registers
Reserved
User Data Memory
Reserved
Memory Mapped Registers
REV. A