ADMCF340BST Analog Devices Inc, ADMCF340BST Datasheet - Page 13

• Manufacturer Part Number: ADMCF340BST
• Manufacturer: Analog Devices Inc

Specifications of ADMCF340BST

• Device Core Size: 16b
• Format: Fixed Point
• Clock Freq (max): 20MHz
• Mips: 20
• Device Input Clock Speed: 20MHz
• Ram Size: 1KB
• Program Memory Size: 12KB
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.44V
• Operating Supply Voltage (max): 2.55V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

Each of the six PWM output signals can be enabled or disabled
by separate output enable bits of the PWMSEG Register. In
addition, three control bits of the PWMSEG Register permit
crossover of the two signals of a PWM.
In Crossover Mode, the high side PWM signals are diverted to
the complementary low side output and low side signals are
diverted to the corresponding high side output.
In many applications, there is a need to provide an isolation
barrier in the gate-drive circuits that turn on the power devices
of the inverter. In general, there are two common isolation
techniques: optical isolation using optocouplers and transformer
isolation using pulse transformers. The PWM controller of the
ADMC(F)340 permits mixing the output PWM signals with a
high frequency chopping signal to permit an easy interface to
such pulse transformers. The features of this gate-drive chopping
mode can be controlled by the PWMGATE Register. There is an
8-bit value within the PWMGATE Register that directly controls
the chopping frequency. In addition, high frequency chopping
can be independently enabled for the high side and the low side
outputs using separate control bits in the PWMGATE Register.
The PWM generator is capable of operating in two distinct modes:
single update mode or double update mode. In single update
mode, the duty cycle values are programmable only once per
PWM period, so that the resultant PWM patterns are symmetrical
about the midpoint of the PWM period. In the double update mode,
a second updating of the PWM duty cycle values is implemented
at the midpoint of the PWM period. In this mode, it is possible
to produce asymmetrical PWM patterns that produce lower
harmonic distortion in three-phase PWM inverters. This technique
also permits the closed-loop controller to change the average
voltage applied to the machine winding at a faster rate, allowing
wider closed-loop bandwidths to be achieved. The operating
mode of the PWM block (single or double update mode) is
selected by a control bit in MODECTRL Register.
The PWM generator of the ADMC(F)340 also provides an internal
signal that synchronizes the PWM switching frequency to the A/D
operation. In single update mode, a PWMSYNC pulse is produced
at the start of each PWM period. In double update mode, an
additional PWMSYNC pulse is produced at the midpoint of
each PWM period. The width of the PWMSYNC pulse is
programmable through the PWMSYNCWT Register.
The PWM signals produced by the ADMC(F)340 can be shut
off in a number of different ways. First, there is a dedicated
asynchronous PWM shutdown pin, PWMTRIP, which, when
brought low, instantaneously places all six PWM outputs in the
OFF state. In addition, PWM shutdown is initiated when the
voltage on any of the three I
thresholds (high or low). Because these two hardware shutdown
mechanisms are asynchronous, and the associated PWM disable
circuitry does not use clocked logic, the PWM will shut down
even if the DSP clock is not running. The PWM system may also
be shut down from software by writing to the PWMSWT Register.
Status information about the PWM system of the ADMC(F)340
is available to the user in the SYSSTAT Register. In particular,
REV. A
SENSE
input pins exceed the trip
–13–
the status of PWMTRIP is available, as well as a status bit that
indicates whether operation is in the first half or the second half
of the PWM period.
A functional block diagram of the PWM controller is shown in
Figure 6. The generation of the six output PWM signals on pins
AH to CL is controlled by four important blocks:
Three-Phase Timing Unit
The 16-bit three-phase timing unit is the core of the PWM con-
troller and produces three pairs of pulsewidth modulated signals
with high resolution and minimal processor overhead. There are
four main configuration registers (PWMTM, PWMDT, PWMPD,
and PWMSYNCWT) that determine the fundamental charac-
teristics of the PWM outputs. In addition, the operating mode of
the PWM (single or double update mode) is selected by Bit 6 of
the MODECTRL Register. These registers, in conjunction with
the three 16-bit duty cycle registers (PWMCHA, PWMCHB, and
PWMCHC), control the output of the three-phase timing unit.
PWM Switching Frequency: PWMTM Register
The PWM switching frequency is controlled by the PWM
period register, PWMTM. The fundamental timing unit of
the PWM controller is T
CLKOUT frequency (DSP instruction rate). Therefore, for a
20 MHz CLKOUT, the fundamental time increment is 50 ns.
The value written to the PWMTM Register is effectively the
number of T
The required PWMTM value is a function of the desired
PWM switching frequency (f
Therefore, the PWM switching period, T
• The three-phase PWM timing unit, which is the core of
• The output control unit allows the redirection of the outputs
• The GATE drive unit provides the high chopping frequency
• The PWM shutdown controller manages the three PWM
• The PWM controller is driven by a clock at the same
the PWM controller, generates three pairs of complemented
and dead-time-adjusted center-based PWM signals.
of the three-phase timing unit for each channel to either the
high side or low side output. In addition, the output control
unit allows individual enabling/disabling of each of the six
PWM output signals.
and its subsequent mixing with the PWM signals.
shutdown modes (via the PWMTRIP pin, the analog block,
or the PWMSWT Register) and generates the correct
RESET signal for the Timing Unit.
frequency as the DSP instruction rate, CLKOUT, and is
capable of generating two interrupts to the DSP core. One
interrupt is generated on the occurrence of a PWMSYNC
pulse, and the other is generated on the occurrence of any
PWM shutdown action.
CK
PWMTM
clock increments in half of a PWM period.
T
S
= ×
2
CK
=
PWMTM T
= 1/f
PWM
2
f
CLKOUT
×
) and is given by:
CLKOUT
f
PWM
×
=
ADMC(F)340
, where f
S
, can be written as:
CK
f
f
CLKIN
PWM
CLKOUT
is the