ADMCF340BST Analog Devices Inc, ADMCF340BST Datasheet
ADMCF340BST
Specifications of ADMCF340BST
Related parts for ADMCF340BST
ADMCF340BST Summary of contents
Page 1
A a TARGET APPLICATIONS Refrigerator and Air Conditioner Compressors, Washing Machines Industrial Variable Speed Drives, HVAC MOTOR TYPES Permanent Magnet Synchronous Motors (PMSM), Brushless DC Motors (BDCM), AC Induction Motors (ACIM), Switched Reluctance Motors (SRM) FEATURES 20 MHz Fixed-Point DSP ...
Page 2
ADMC(F)340 ANALOG-TO-DIGITAL CONVERTER Parameter Signal Input 1 Resolution 2 Linearity Error 3 Zero Offset Comparator Delay 2 ADC High Level Input Current 2 ADC Low Level Input Current NOTES 1 Resolution varies with PWM switching frequency (double update mode) 78.1 ...
Page 3
VOLTAGE REFERENCE Parameter Voltage Level (V ) REF Drift Specifications subject to change without notice. POWER-ON RESET Parameter Reset Threshold Hysteresis Reset Active Timeout Period 16 *2 CLKOUT cycles. Specifications subject to change without notice. ELECTRICAL CHARACTERISTICS Symbol Parameter V ...
Page 4
ADMC(F)340 TIMING PARAMETERS Parameter Clock Signals Signal T is defined as 0 The ADMC(F)340 uses an input clock with CK CKIN a frequency equal to half the instruction rate MHz input clock (which is equivalent to ...
Page 5
TIMING PARAMETERS Parameter Serial Ports Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP IN Switching Characteristics: t CLKOUT High to SCLK CC t SCLK ...
Page 6
ADMC(F)340 ABSOLUTE MAXIMUM RATINGS* Supply Voltage ( –0 +7 Supply Voltage ( ...
Page 7
Pin No. Mnemonic 1 AGND 2 DGND1 RESET 3 4 PB6 PB7 7 PB8 PB9 10 PB10 PB11 13 PB12 ...
Page 8
ADMC(F)340 (continued from page 1) External PWMTRIP Pin Switched Reluctance Motor Mode Selection Pin PWM Polarity Selection Pin Integrated 13-Channel ADC Subsystem 3 Bipolar I Inputs with Programmable SENSE Sample-and-Hold Amplifier and Overcurrent Protection (Usable as 3 Dedicated Analog Inputs) ...
Page 9
DSP CORE ARCHITECTURE OVERVIEW Figure overall block diagram of the DSP core of the ADMC(F)340. The flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle (50 ns ...
Page 10
ADMC(F)340 • SPORT0 has one pin, SCLK0, shared with SPORT1. During a boot phase (SPORT1 Boot Mode enabled by a bit in the MODECTRL Register), the serial clock of SPORT1 is externally available. The serial clock of SPORT0 is externally ...
Page 11
FLASH MEMORY SUBSYSTEM The ADMC(F)340 has 4K × 24-bit user-programmable, nonvola- tile flash memory. A flash programming utility is provided with the development tools and performs the basic device programming operations: erase, program, and verify. The flash memory array is ...
Page 12
ADMC(F)340 Reset The ADMC(F)340 DSP core and peripherals must be correctly reset when the device is powered up to ensure proper unitization. The ADMC(F)340 contains an integrated power-on-reset (POR) circuit that provides a complete system reset on power-up and power-down. ...
Page 13
Each of the six PWM output signals can be enabled or disabled by separate output enable bits of the PWMSEG Register. In addition, three control bits of the PWMSEG Register permit crossover of the two signals of a PWM. In ...
Page 14
ADMC(F)340 For example, for a 20 MHz CLKOUT and a desired PWM = 100 µs), the correct value switching frequency of 10 kHz ( load into the PWMTM Register is: × PWMTM × ...
Page 15
T (corresponding 12.8 µs for a CLKOUT to 256 T CK rate of 20 MHz). Following a reset, the PWMSYNCWT Register contains 0x27 (= 39) ...
Page 16
ADMC(F)340 In general, the on-times of the PWM signals in double update mode are defined by (PWMCHA + PWMCHA – PWMDT (PWMTM + PWMTM – PWMCHA × T PWMDT ...
Page 17
Table V. Achievable PWM Resolution in Single and Double Update Modes Resolution Single Update Mode (Bit) PWM Frequency (kHz) 8 39.1 9 19.5 10 9.8 11 4.9 12 2.4 Minimum Pulsewidth: PWMPD Register In many power converter switching applications, it ...
Page 18
ADMC(F)340 PWMCHA = PWMCHB AH 2 PWMDT PWMTM Figure 9. An example of PWM signals suitable for ECM control. PWMCHA = PWMCHB, BH/BL are a crossover pair. AL, BH, CH, and CL outputs are disabled. ...
Page 19
SWITCHED RELUCTANCE MODE The PWM block of the ADMC(F)340 contains a switched reluctance (SR) mode that is controlled by the PWMSR pin. The switched reluctance mode is enabled by connecting the PWMSR pin to DGND. In this SR mode, the ...
Page 20
ADMC(F)340 MODECTRL REG <09..10..11> ICONST VOLTAGE CHANNEL 1 V1 CURRENT COMP VOLTAGE CHANNEL 2 V2 CURRENT COMP VOLTAGE CHANNEL 3 V3 CURRENT COMP VAUX0 (V) VAUX0 VAUX1 (V) VAUX1 VAUX2 (V) VAUX2 COMP 8-1 VAUX4 (V) VAUX4 MULTIPLEXER VAUX5 (V) ...
Page 21
VIL T VIL T – T PWM CRST PWMSYNC COMPARATOR OUTPUT Figure 12. Analog Input Block Operation The ADC system consists of four comparators and a single timer that may be clocked at either the DSP rate ...
Page 22
ADMC(F)340 Analog Front End The main analog inputs of the ADMC(F)340 ( are connected to the ADC converter through three SENSE3 front end blocks. Figure 14 shows the block diagram of a single analog front end. Each analog ...
Page 23
Table IX. Fundamental Characteristics of Auxiliary PWM Timer of ADMC(F)340 Parameter Test Conditions Resolution PWM Frequency 10 MHz CLKIN AUXILIARY PWM TIMERS Overview The ADMC(F)340 provides two variable frequency, variable duty cycle, 16-bit, auxiliary PWM outputs that are available at ...
Page 24
ADMC(F)340 2 (AUXTM0 + 1) 2 AUXCH0 AUX0 2 (AUXTM0 + 1) AUX1 2 AUXCH1 2 (AUXTM1 + 1) 17b. Typical Auxiliary PWM Signal (All Times in Increments – Offset Mode CK WATCHDOG TIMER The ADMC(F)340 incorporates ...
Page 25
PWMTRIP interrupts and PORTA_FLAG Register for the PIO interrupts. Table X. Interrupt Vector Addresses Interrupt Source Interrupt Vector Address PWMTRIP 0x002C (Highest Priority) Peripheral Interrupt (IRQ2) 0x0004 PWMSYNC 0x000C PIO 0x0008 Software Interrupt 1 0x0018 Software Interrupt 0 0x001C ...
Page 26
ADMC(F)340 With SPORT1 configured in UART mode, the SPORT0 serial clock (SCLK0) is externally available through the SCLK1/ SCLK0 pin. The SPORT1 data transmit (DT1) is externally available through the FL1/DT1 pin. SPORT0 Configuration SPORT0 can be configured in SPORT, ...
Page 27
SPORT I/O Signal DT0 (Data Transmit) DR0 TFS0 RFS0 SCLK0 SCK CYCLE # SCK (POLARITY = 0) SCK (POLARITY = 1) SS MOSI SEE NOTE 1 MISO SEE NOTE 2 NOTES 1. LSB OF PREVIOUSLY TRANSMITTED WORD 2. UNDEFINED Figure ...
Page 28
ADMC(F)340 Address (HEX) Name 0x2000 ADC1 0x2001 ADC2 0x2002 ADC3 0x2003 ADCAUX 0x2004 PORTA_DIR 0x2005 PORTA_DATA 0x2006 PORTA_INTEN 0x2007 PORTA_FLAG 0x2008 PWMTM 0x2009 PWMDT 0x200A PWMPD 0x200B PWMGATE 0x200C PWMCHA 0x200D PWMCHB 0x200E PWMCHC 0x200F PWMSEG 0x2010 AUXCH0 0x2011 AUXCH1 ...
Page 29
Address Name 0x3FFA SPORT0_Rx_Words1 0x3FF9 SPORT0_Rx_Words0 0x3FF8 SPORT0_Tx_Words1 0x3FF7 SPORT0_Tx_Words0 0x3FF6 SPORT0_CTRL_REG 0x3FF5 SPORT0_SCLKDIV 0x3FF4 SPORT0_RFSDIV 0x3FF3 SPORT0_AUTOBUF CTRL 0x3FF2 SPORT1_CTRL_REG 0x3FFF SYSCNTL 0x3FFE MEMWAIT 0x3FFD TPERIOD 0x3FFC TCOUNT 0x3FFB TSCALE 0x3FFA . . . F3 0x3FF2 SPORT1_CTRL_REG 0x3FF1 SPORT1_SCLKDIV ...
Page 30
ADMC(F)340 BOOT-FROM-FLASH-CODE RESERVED ALWAYS READ 0 MOST SIGNIFICANT BIT IS ON THE LEFT. FOR EXAMPLE, DATA23 IS BIT 15 OF FMDRH. Figure 21. Configuration of Flash Memory Registers Default bit values are shown value is shown, the bit ...
Page 31
A CHANNEL CROSSOVER CROSSOVER B CHANNEL CROSSOVER 1 = CROSSOVER C CHANNEL CROSSOVER Default bit values are shown; if ...
Page 32
ADMC(F)340 LOW SIDE GATE CHOPPING 0 = DISABLE 1 = ENABLE HIGH SIDE GATE CHOPPING Figure 23. Configuration of ...
Page 33
CLOCKOUT 1 = AUX0 0 = PWMSYNC 1 ...
Page 34
ADMC(F)340 Figure 25. Configuration of Additional PIO Registers Default bit values are shown value ...
Page 35
...
Page 36
ADMC(F)340 15 0 SPORT SPORT MODE MODE SELECT 1 = UART MODE SPORT SPORT SPI MODE 1 = SP1 MODE 0 = STANDARD SPI CLOCK 1 = REVERSE POLARITY 0 = PHA0 SPI CLOCK ...
Page 37
Selection VAUX0 (1) VAUX1 (1) VAUX2 (1) V (1) REF VAUX4 VAUX5 VAUX6 VAUX7 REV. A Table XIV. Auxiliary Analog Input Selection MODECTRL (5) MODECTRL ( ...
Page 38
ADMC(F)340 0 = DISABLE 1 = ENABLE 15 0 INTERRUPT FORCE IRQ2 SPORT0 TRANSMIT SPORT0 RECEIVE SOFTWARE 1 SOFTWARE 0 SPORT1 TRANSMIT OR IRQ1 SPORT1 RECEIVE OR IRQ0 TIMER PERIPHERAL (OR IRQ2) ...
Page 39
DISABLED SPORT1 ENABLE 1 = ENABLED Default bit values are shown value is shown, the bit field is undefined at reset. REV. A SYSCNTL (R/ ...
Page 40
ADMC(F)340 10 6 1.45 2 1.40 1.35 SEATING PLANE VIEW A ROTATED 90 CCW Revision History Location 10/02—Data Sheet changed from REV REV. A. Changed ADMCF340 to ADMC(F)340 ...................................................................................................................... UNIVERSAL Changes to PRODUCT TITLE .......................................................................................................................................................1 Changes to FEATURES ...