ADMCF340BST Analog Devices Inc, ADMCF340BST Datasheet - Page 16

• Manufacturer Part Number: ADMCF340BST
• Manufacturer: Analog Devices Inc

Specifications of ADMCF340BST

• Device Core Size: 16b
• Format: Fixed Point
• Clock Freq (max): 20MHz
• Mips: 20
• Device Input Clock Speed: 20MHz
• Ram Size: 1KB
• Program Memory Size: 12KB
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.44V
• Operating Supply Voltage (max): 2.55V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

ADMC(F)340
In general, the on-times of the PWM signals in double update
mode are defined by:
T
T
Because of the completely general case in double update mode,
the switching period is given by:
Again, the values of T
zero and T
16-BIT PWM TIMER
Parameter
Counter Resolution
Edge Resolution (Single Update Mode)
Edge Resolution (Double Update Mode)
Programmable Dead Time Range
Programmable Dead Time Increments
Programmable Pulse Deletion Range
Programmable Pulse Deletion Increments
PWM Frequency Range
PWMSYNC Pulsewidth (T
Gate Drive Chop Frequency Range
PWMDT
AH
AL
= (PWMTM
= (PWMCHA
d
d
1
AH
AL
S
– PWMDT
.
T
=
−
=
–
S
=
=
(
PWMTM
(
PWMCHA
=
PWMDT
PWMCHA
T
PWMTM
T
PWMTM
T
1
T
(
AL
AH
1
S
+ PWMTM
PWNMTM
S
+ PWMCHA
Table IV. Fundamental Characteristics of PWM Generation Unit of ADMC(F)340
AH
2
PWMTM
PWMTM
) × T
and T
1
1
1
1
1
+
+
2
+
+
+
CK
PWMDT
PWMTM
+
PWMTM
CRST
PWMCHA
PWMTM
2
1
PWMDT
AL
– PWMCHA
+
2
1
– PWMDT
1
are constrained to lie between
PWMTM
+
)
+
PWMTM
PWMTM
2
2
2
2
1
2
+
+
PWMCHA
PWMDT
1
1
2
)
– PWMDT
– PWMCHA
2
×
2
T
CK
2
)
1
)
2
) × T
2
–
CK
–16–
PWM signals similar to those illustrated in Figures 7 and 8 can
be produced on the BH, BL, CH, and CL outputs by program-
ming the PWMCHB and PWMCHC Registers in a manner
identical to that described for PWMCHA.
The PWM controller does not produce any PWM outputs until
all of the PWMTM, PWMCHA, PWMCHB, and PWMCHC
Registers have been written to at least once. After these registers
have been written to, the counters in the three-phase timing unit
are enabled. Writing to these registers also starts the main PWM
timer. If, during initialization, the PWMTM Register is written
to before the PWMCHA, PWMCHB, and PWMCHC Registers,
the first PWMSYNC pulse (and interrupt if enabled) will be gener-
ated (1.5 × T
PWMTM Register in single update mode. In double update mode,
the first PWMSYNC pulse will be generated (T
seconds after the initial write to the PWMTM Register in single
update mode.
Effective PWM Resolution
In single update mode, the same values of PWMCHA, PWMCHB,
and PWMCHC are used to define the on-times in both half
cycles of the PWM period. As a result, the effective resolution of
the PWM generation process is 2 T
CLKOUT) since incrementing one of the duty cycle registers by
1 changes the resultant on-time of the associated PWM signals
by T
In double update mode, improved resolution is possible since
different values of the duty cycle registers are used to define the
on-times in both the first and second halves of the PWM period.
As a result, it is possible to adjust the on-time over the whole
period in increments of T
PWM resolution of T
20 MHz CLKOUT).
CK
in each half period (or 2 T
CK
Min
0
153
0.05
0.02
× PWMTM) seconds after the initial write to the
CK
in double update mode (or 50 ns for a
Typ
16
100
50
100
0
50
CK
. This corresponds to an effective
CK
CK
for the full period).
(or 100 ns for a 20 MHz
Max
102
51
12.8
5
CK
× PWMTM)
Unit
Bits
ns
ns
µs
ns
µs
ns
Hz
µs
MHz
REV. A