ADMCF340BST Analog Devices Inc, ADMCF340BST Datasheet - Page 23

• Manufacturer Part Number: ADMCF340BST
• Manufacturer: Analog Devices Inc

Specifications of ADMCF340BST

• Device Core Size: 16b
• Format: Fixed Point
• Clock Freq (max): 20MHz
• Mips: 20
• Device Input Clock Speed: 20MHz
• Ram Size: 1KB
• Program Memory Size: 12KB
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.44V
• Operating Supply Voltage (max): 2.55V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

Parameter
Resolution
PWM Frequency
AUXILIARY PWM TIMERS
Overview
The ADMC(F)340 provides two variable frequency, variable duty
cycle, 16-bit, auxiliary PWM outputs that are available at the
AUX1 and AUX0 pins. When enabled, these auxiliary PWM
outputs can be used to provide switching signals to other circuits in
a typical motor control system such as power factor corrected
front-end converters or other switching power converters. Alterna-
tively, by adding a suitable filter network, the auxiliary PWM
output signals can be used as simple single-bit digital-to-analog
converters, which is shown in Figure 16. The auxiliary PWM
system of the ADMC(F)340 can operate in two different modes:
independent mode or offset mode. The operating mode of the
auxiliary PWM system is controlled by Bit 8 of the MODECTRL
Register. Setting Bit 8 of the MODECTRL Register places the
auxiliary PWM system in the independent mode. In this mode,
the two auxiliary PWM generators are completely independent
and separate switching frequencies and duty cycles may be
programmed for each auxiliary PWM output. In this mode, the
16-bit AUXTM0 Register sets the switching frequency of the
signal at the AUX0 output pin. Similarly, the 16-bit AUXTM1
Register sets the switching frequency of the signal at the AUX1
pin. The fundamental time increment for the auxiliary PWM
outputs is twice the DSP instruction rate (or 2 T
corresponding switching periods are given by:
Since the values in both AUXTM0 and AUXTM1 can range
from 0 to 0xFFFF, the achievable switching frequency of the
auxiliary PWM signals may range from 152.59 Hz to 10 MHz
for a CLKOUT frequency of 20 MHz. The on-time of the two
auxiliary PWM signals is programmed by the two 16-bit AUXCH0
and AUXCH1 Registers, according to:
so that output duty cycles from 0% to 100% are possible. Duty
cycles of 100% are produced if the on-time value exceeds the
period value. Typical auxiliary PWM waveforms in independent
mode are shown in Figure 17(a). When Bit 8 of the MODECTRL
Register is cleared, the auxiliary PWM channels are placed in
offset mode. In offset mode, the switching frequency of the two
signals on the AUX0 and AUX1 pins are identical and controlled
by AUXTM0 in a manner similar to that previously described
for independent mode. In addition, the on-times of both the
AUX0 and AUX1 signals are controlled by the AUXCH0 and
AUXCH1 Registers as before.
REV. A
T
T
T
T
ON,
ON,
AUX
AUX
AUX
AUX
1
0
= ×
= ×
2
2
1 2
Table IX. Fundamental Characteristics of Auxiliary PWM Timer of ADMC(F)340
0
=
=
(
(
AUXTM
AUXTM
2
×
×
(
(
AUXCH
AUXCH
1 1
0 1
Test Conditions
10 MHz CLKIN
+
+
)
1
0
)
)
×
)
×
×
T
×
T
T
CK
CK
T
CK
CK
CK
) and the
–23–
However in this mode, the AUXTM1 Register defines the offset
time from the rising edge of the signal on the AUX0 pin to that
on the AUX1 pin according to:
For correct operation in this mode, the value written to the
AUXTM1 Register must be less than the value written to the
AUXTM0 Register. Typical auxiliary PWM waveforms in offset
mode are shown in Figure 17(b). Again, duty cycles from 0% to
100% are possible in this mode.
In both operating modes, the resolution of the auxiliary PWM
system is 16 bits only at the minimum switching frequency
(AUXTM0 = AUXTM1 = 65535 in independent mode,
AUXTM0 = 65535 in offset mode). Obviously, as the switching
frequency is increased, the resolution is reduced.
Values can be written to the auxiliary PWM Registers at any
time. However, new duty cycle values written to the AUXCH0
and AUXCH1 Registers only become effective at the start of the
next cycle. Writing to the AUXTM0 or AUXTM1 Registers
causes the internal timers to be reset to 0 and new PWM cycles
to begin. By default following a reset, Bit 8 of the MODECTRL
Register is cleared, thus enabling offset mode. In addition, the
registers AUXTM0 and AUXTM1 default to 0xFFFF, corre-
sponding to the minimum switching frequency and zero offset.
The on-time registers AUXCH0 and AUXCH1 default to 0x0000.
Auxiliary PWM Interface, Registers, and Pins
The registers of the auxiliary PWM system are summarized in
Figure 26.
AUX0
AUX1
17a. Typical Auxiliary PWM Signal (All Times in
Increments of T
Min
0.152
Figure 16. Auxiliary PWM Output Filter
T
2
OFFSET
AUXCH0
AUXPWM
CK
= ×
) – Independent Mode
2
2
Typ
16
AUXCH1
R1 = R2 = 13k
C1 = C2 = 10nF
(
R1
AUXTM
2
C1
(AUXTM0 + 1)
R2
2
1 1
Max
ADMC(F)340
+
C2
(AUXTM1 + 1)
2
)
×
AUXCH1
T
CK
Unit
Bits
MHz