AD7792BRUZ Analog Devices Inc, AD7792BRUZ Datasheet - Page 20

• Manufacturer Part Number: AD7792BRUZ
• Description: IC ADC 16BIT SIG-DEL 3CH 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7792BRUZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 16
• Sampling Rate (per Second): 500
• Number Of Converters: 1
• Power Dissipation (max): 2.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 16bit
• Sampling Rate: 470SPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 2.7V To 5.25V
• Supply Voltage Range - Digital: 2.7V To 5.25V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7792EBZ - BOARD EVALUATION FOR AD7792
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD7792/AD7793
ADC CIRCUIT INFORMATION
OVERVIEW
The AD7792/AD7793 are low power ADCs that incorporate a
∑-Δ modulator, a buffer, reference, in-amp, and an on-chip
digital filter intended for the measurement of wide dynamic
range, low frequency signals such as those in pressure
transducers, weigh scales, and temperature measurement
applications.
The part has three differential inputs that can be buffered or
unbuffered. The device can be operated with the internal 1.17 V
reference, or an external reference can be used. Figure 12 shows
the basic connections required to operate the part.
THERMOCOUPLE
The output rate of the AD7792/AD7793 (f
mable. The allowable update rates, along with their corresponding
settling times, are listed in Table 16. Normal mode rejection is
the major function of the digital filter. Simultaneous 50 Hz and
60 Hz rejection is optimized when the update rate equals
16.7 Hz or less as notches are placed at both 50 Hz and 60 Hz
with these update rates. See Figure 14.
The AD7792/AD7793 use slightly different filter types,
depending on the output update rate so that the rejection of
quantization noise and device noise is optimized. When the
update rate is from 4.17 Hz to 12.5 Hz, a Sinc3 filter, along with
an averaging filter, is used. When the update rate is from
16.7 Hz to 39 Hz, a modified Sinc3 filter is used. This filter
provides simultaneous 50 Hz/60 Hz rejection when the update
rate equals 16.7 Hz. A Sinc4 filter is used when the update rate
is from 50 Hz to 242 Hz. Finally, an integrate-only filter is used
when the update rate equals 470 Hz.
Figure 13 to Figure 16 show the frequency response of the
different filter types for several update rates.
JUNCTION
R
R
C
AIN1(+)
AIN1(–)
R
REF
Figure 12. Basic Connection Diagram
AIN2(+)
AIN2(–)
REFIN(+)
REFIN(–)
IOUT2
V
BIAS
GND
MUX
AV
AV
GND
DD
DD
AV
DD
BUF
REFERENCE
BAND GAP
IN-AMP
ADC
INTERNAL
CLOCK
CLK
) is user-program-
REFIN(+) REFIN(–)
ADC
Σ-Δ
GND
AD7792/AD7793
INTERFACE
CONTROL
SERIAL
LOGIC
AND
Rev. B | Page 20 of 32
DOUT/RDY
DIN
SCLK
CS
DV
DD
–100
–100
–100
–20
–40
–60
–80
–20
–40
–60
–80
–20
–40
–60
–80
0
0
0
0
0
0
20
Figure 13. Filter Profile with Update Rate = 4.17 Hz
Figure 14. Filter Profile with Update Rate = 16.7 Hz
Figure 15. Filter Profile with Update Rate = 242 Hz
500
20
40
60
1000
40
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
80
1500
100
60
120
2000
80
140
160
2500
100
180
3000
120
200