AD7792BRUZ Analog Devices Inc, AD7792BRUZ Datasheet - Page 14

• Manufacturer Part Number: AD7792BRUZ
• Description: IC ADC 16BIT SIG-DEL 3CH 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7792BRUZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 16
• Sampling Rate (per Second): 500
• Number Of Converters: 1
• Power Dissipation (max): 2.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 16bit
• Sampling Rate: 470SPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 2.7V To 5.25V
• Supply Voltage Range - Digital: 2.7V To 5.25V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7792EBZ - BOARD EVALUATION FOR AD7792
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD7792/AD7793
ON-CHIP REGISTERS
The ADC is controlled and configured via a number of on-chip
registers, which are described on the following pages. In the
following descriptions, set implies a Logic 1 state and cleared
implies a Logic 0 state, unless otherwise stated.
COMMUNICATIONS REGISTER
RS2, RS1, RS0 = 0, 0, 0
The communications register is an 8-bit write-only register. All
communications to the part must start with a write operation to
the communications register. The data written to the
communications register determines whether the next
operation is a read or write operation, and to which register this
operation takes place. For read or write operations, once the
subsequent read or write operation to the selected register is
CR7
WEN(0)
Table 11. Communications Register Bit Designations
Bit Location
CR7
CR6
CR5 to CR3
CR2
CR1 to CR0
Table 12. Register Selection
RS2
0
0
0
0
0
1
1
1
1
RS1
0
0
0
1
1
0
0
1
1
Bit Name
WEN
R/W
RS2 to
RS0
CREAD
0
RS0
0
0
1
0
1
0
1
0
1
CR6
R/W(0)
Register
Communications Register During a Write Operation
Status Register During a Read Operation
Mode Register
Configuration Register
Data Register
ID Register
IO Register
Offset Register
Full-Scale Register
Description
Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually
occurs. If a 1 is the first bit written, the part does not clock on to subsequent bits in the register. It stays at this
bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits are loaded to
the communications register.
A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position
indicates that the next operation is a read from the designated register.
Register Address Bits. These address bits are used to select which of the ADC’s registers are being selected
during this serial interface communication. See Table 12.
Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial
interface is configured so that the data register can be continuously read. For example, the contents of the
data register are placed on the DOUT pin automatically when the SCLK pulses are applied after the RDY pin
goes low to indicate that a conversion is complete. The communications register does not have to be written
to for data reads. To enable continuous read mode, the instruction 01011100 must be written to the
communications register. To exit the continuous read mode, the instruction 01011000 must be written to the
communications register while the RDY pin is low. While in continuous read mode, the ADC monitors activity
on the DIN line so that it can receive the instruction to exit continuous read mode. Additionally, a reset occurs
if 32 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an
instruction is to be written to the device.
These bits must be programmed to Logic 0 for correct operation.
CR5
RS2(0)
CR4
RS1(0)
Rev. B | Page 14 of 32
CR3
RS0(0)
complete, the interface returns to where it expects a write
operation to the communications register. This is the default
state of the interface and, on power-up or after a reset, the ADC
is in this default state waiting for a write operation to the
communications register. In situations where the interface
sequence is lost, a write operation of at least 32 serial clock
cycles with DIN high returns the ADC to this default state by
resetting the entire part. Table 11 outlines the bit designations
for the communications register. CR0 through CR7 indicate the
bit location, CR denoting the bits are in the communications
register. CR7 denotes the first bit of the data stream. The
number in parentheses indicates the power-on/reset default
status of that bit.
CR2
CREAD(0)
Register Size
8-bit
8-bit
16-bit
16-bit
16-/24-bit
8-bit
8-bit
16-bit (AD7792)/24-bit (AD7793)
16-bit (AD7792)/24-bit (AD7793)
CR1
0(0)
CR0
0(0)