AD7792BRUZ Analog Devices Inc, AD7792BRUZ Datasheet - Page 16

• Manufacturer Part Number: AD7792BRUZ
• Description: IC ADC 16BIT SIG-DEL 3CH 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7792BRUZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 16
• Sampling Rate (per Second): 500
• Number Of Converters: 1
• Power Dissipation (max): 2.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 16bit
• Sampling Rate: 470SPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 2.7V To 5.25V
• Supply Voltage Range - Digital: 2.7V To 5.25V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7792EBZ - BOARD EVALUATION FOR AD7792
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD7792/AD7793
Table 15. Operating Modes
MD2
0
0
0
0
1
1
1
1
Table 16. Update Rates Available
FS3
0
0
0
0
0
0
0
0
1
MD1
0
0
1
1
0
0
1
1
FS2
0
0
0
0
1
1
1
1
0
MD0
0
1
0
1
0
1
0
1
FS1
0
0
1
1
0
0
1
1
0
Mode
Continuous Conversion Mode (Default).
In continuous conversion mode, the ADC continuously performs conversions and places the result in the data
register. RDY goes low when a conversion is complete. The user can read these conversions by placing the device in
continuous read mode, whereby the conversions are automatically placed on the DOUT line when SCLK pulses are
applied. Alternatively, the user can instruct the ADC to output the conversion by writing to the communications
register. After power-on, a channel change, or a write to the mode, configuration, or IO registers, the first conversion
is available after a period of 2/f
Single Conversion Mode.
When single conversion mode is selected, the ADC powers up and performs a single conversion. The oscillator
requires 1 ms to power up and settle. The ADC then performs the conversion, which takes a time of 2/f
conversion result is placed in the data register, RDY goes low, and the ADC returns to power-down mode. The
conversion remains in the data register, and RDY remains active low until the data is read or another conversion is
performed.
Idle Mode.
In idle mode, the ADC filter and modulator are held in a reset state, although the modulator clocks are still provided.
Power-Down Mode.
In power-down mode, all the AD7792/AD7793 circuitry is powered down, including the current sources, burnout
currents, bias voltage generator, and CLKOUT circuitry.
Internal Zero-Scale Calibration.
An internal short is automatically connected to the enabled channel. A calibration takes 2 conversion cycles to
complete. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The
ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of
the selected channel.
Internal Full-Scale Calibration.
A full-scale input voltage is automatically connected to the selected analog input for this calibration.
When the gain equals 1, a calibration takes 2 conversion cycles to complete. For higher gains, 4 conversion cycles
are required to perform the full-scale calibration.
RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed
in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the
selected channel.
Internal full-scale calibrations cannot be performed when the gain equals 128. With this gain setting, a system full-
scale calibration can be performed.
A full-scale calibration is required each time the gain of a channel is changed to minimize the full-scale error.
System Zero-Scale Calibration.
User should connect the system zero-scale input to the channel input pins as selected by the CH2 to CH0 bits. A
system offset calibration takes 2 conversion cycles to complete. RDY goes high when the calibration is initiated and
returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured
offset coefficient is placed in the offset register of the selected channel.
System Full-Scale Calibration.
User should connect the system full-scale input to the channel input pins as selected by the CH2 to CH0 bits.
A calibration takes 2 conversion cycles to complete. RDY goes high when the calibration is initiated and returns low
when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale
coefficient is placed in the full-scale register of the selected channel.
A full-scale calibration is required each time the gain of a channel is changed.
FS0
0
1
0
1
0
1
0
1
0
f
x
470
242
123
62
50
39
33.2
19.6
ADC
(Hz)
ADC
t
x
4
8
16
32
40
48
60
101
. Subsequent conversions are available at a frequency of f
SETTLE
Rev. B | Page 16 of 32
(ms)
Rejection @ 50 Hz/60 Hz (Internal Clock)
90 dB (60 Hz only)
ADC
.
ADC
. The