LTC2408CG Linear Technology, LTC2408CG Datasheet - Page 14

• Manufacturer Part Number: LTC2408CG
• Description: IC A/D CONV 24BIT 8-CHAN 28-SSOP
• Manufacturer: Linear Technology

Specifications of LTC2408CG

• Number Of Bits: 24
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS
LTC2404/LTC2408
Channel Selection
Typically, CSADC and CSMUX are tied together or CSADC
is inverted and drives CSMUX. SCK and CLK are tied
together and driven with a common clock signal. During
channel selection, CSMUX is HIGH. Data is shifted into the
D
shows the bit combinations for channel selection. In order
to enable the multiplexer output, CSMUX must be pulled
LOW. The multiplexer should be programmed after the
previous conversion is complete. In order to guarantee the
conversion is complete, the multiplexer addressing should
be delayed a minimum t
60Hz notch) after the data out is read.
While the multiplexer is being programmed, the ADC is in
a low power sleep state. Once the MUX addressing is
complete, the data from the preceding conversion can be
read. A new conversion cycle is initiated following the data
read cycle with the analog input tied to the newly selected
channel.
14
Table 2. LTC2404/LTC2408 Output Data Format
Input Voltage
V
9/8 • V
V
V
3/4V
3/4V
1/2V
1/2V
1/4V
1/4V
0
–1LSB
–1/8 • V
V
*The sub LSBs are valid conversion results beyond the 24-bit level that may be included in averaging or discarded without loss of resolution.
**The sign bit changes state during the 0 code.
+
IN
REF
REF
IN
IN
/0
> 9/8 • V
< –1/8 • V
–
REF
REF
REF
REF
REF
REF
pin on the rising edge of CLK, see Figure 3. Table 3
+ 1LSB
REF
REF
+ 1LSB
+ 1LSB
+ 1LSB
REF
REF
Bit 31
U
EOC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CONV
INFORMATION
U
Bit 30
DMY
(approximately 133ms for a
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Bit 29
1/0**
SIG
1
1
1
1
1
1
1
1
1
1
0
0
0
Bit 28
EXR
1
1
1
0
0
0
0
0
0
0
0
1
1
1
U
Bit 27
MSB
0
0
0
1
1
1
1
0
0
0
0
1
1
1
Bit 26
Table 3. Logic Table for Channel Selection
*Not used for the LTC2404.
Frequency Rejection Selection (F
The LTC2404/LTC2408 internal oscillator provides better
than 110dB normal mode rejection at the line frequency
and all its harmonics for 50Hz 2% or 60Hz 2%. For
60Hz rejection, F
(Pin 1) while for 50Hz rejection the F
connected to V
CHANNEL STATUS
0
0
0
1
1
0
0
1
1
0
0
1
1
1
All Off
CH4*
CH5*
CH6*
CH7*
CH0
CH1
CH2
CH3
Bit 25
0
0
0
1
0
1
0
1
0
1
0
1
1
1
CC
Bit 24
O
(Pin 2).
1
1
0
1
0
1
0
1
0
1
0
1
0
0
(Pin 26) should be connected to GND
EN
0
1
1
1
1
1
1
1
1
Bit 23
1
1
0
1
0
1
0
1
0
1
0
1
0
0
D2
X
0
0
0
0
1
1
1
1
…
...
...
...
...
...
...
...
...
...
...
...
...
...
...
O
Pin Connection)
O
Bit 4
LSB
D1
pin should be
X
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
SUB LSBs*
Bit 3-0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D0
X
0
1
0
1
0
1
0
1