MAX1198ECM+D Maxim Integrated Products, MAX1198ECM+D Datasheet - Page 5

IC ADC 8BIT 100MSPS DUAL 48-TQFP

MAX1198ECM+D

Manufacturer Part Number
MAX1198ECM+D
Description
IC ADC 8BIT 100MSPS DUAL 48-TQFP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX1198ECM+D

Number Of Bits
8
Sampling Rate (per Second)
100M
Data Interface
Parallel
Number Of Converters
2
Power Dissipation (max)
314mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
Conversion Rate
100 MSPs
Resolution
8 bit
Snr
48.5 dB
Voltage Reference
2.048 V
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Power Dissipation
1000 mW
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Input Voltage
3.3 V
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ELECTRICAL CHARACTERISTICS (continued)
(V
10kΩ resistor, V
otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at
T
A
Input Low Threshold
Input Hysteresis
Input Leakage
Input Capacitance
DIGITAL OUTPUTS ( D7A–D0A, D7B–D0B)
Output Voltage Low
Output Voltage High
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
Analog Supply Current
Output Supply Current
Analog Power Dissipation
Power-Supply Rejection
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Time
OE Fall to Output Enable Time
OE Rise to Output Disable Time
CLK Pulse Width High
CLK Pulse Width Low
DD
= +25°C.)
= 3.3V, OV
with Internal Reference and Parallel Outputs
PARAMETER
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
IN
DD
= 2V
= 2.5V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
_______________________________________________________________________________________
P-P
(differential with respect to COM), C
SYMBOL
t
t
DISABLE
ENABLE
PDISS
V
I
OV
PSRR
I
C
OVDD
I
V
LEAK
V
V
C
t
HYST
VDD
t
V
t
I
OUT
DO
I
CH
CL
OH
DD
IH
OL
IL
IN
IL
DD
CLK
PD, OE, SLEEP, T/B
V
V
I
I
OE = OV
OE = OV
C
Operating, f
applied to both channels
Sleep mode
Shutdown, clock idle, PD = OE = OV
Operating, f
applied to both channels (Note 6)
Sleep mode
Shutdown, clock idle, PD = OE = OV
Operating, f
applied to both channels
Sleep mode
Shutdown, clock idle, PD = OE = OV
Offset, V
Gain, V
C
Clock period: 10ns (Note 7)
Clock period: 10ns (Note 7)
SINK
SOURCE
IH
IL
L
L
= 15pF
= 20pF (Notes 1, 7)
= 0
= V
= -200µA
DD
DD
DD
DD
DD
= 200µA
= OV
±5%
INA & B
INA & B
INA & B
±5%
L
= 10pF at digital outputs, f
CONDITIONS
DD
= 20MHz at -1dB FS
= 20MHz at -1dB FS
= 20MHz at -1dB FS
DD
DD
DD
CLK
= 100MHz, T
OV
MIN
0.2
2.7
1.7
DD
-
5 ± 0.5
5 ± 0.5
T YP
0.15
0.15
11.5
10.6
264
3.3
2.5
3.2
0.5
80
±3
±3
A
5
5
2
2
6
5
5
= T
MIN
OV
MAX
0.2 ×
0.2 ×
8.25
V
±20
±20
±10
314
0.2
3.6
3.6
95
20
10
66
to T
DD
DD
MAX
UNITS
, unless
mV/V
mW
mA
mA
µW
µA
pF
µA
pF
µA
µA
ns
ns
ns
ns
ns
V
V
V
V
V
V
5

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