MAX1198ECM+D Maxim Integrated Products, MAX1198ECM+D Datasheet - Page 14

• Manufacturer Part Number: MAX1198ECM+D
• Description: IC ADC 8BIT 100MSPS DUAL 48-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1198ECM+D

• Number Of Bits: 8
• Sampling Rate (per Second): 100M
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 314mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Conversion Rate: 100 MSPs
• Resolution: 8 bit
• Snr: 48.5 dB
• Voltage Reference: 2.048 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Power Dissipation: 1000 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 3.3 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 4. Output Timing Diagram
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
The MAX1198 clock input operates with a voltage thresh-
old set to V
than 50% must meet the specifications for high and low
periods as stated in the Electrical Characteristics table.
Figure 3 depicts the relationship between the clock
input, analog input, and data output. The MAX1198
samples at the rising edge of the input clock. Output
data for channels A and B is valid on the next rising
edge of the input clock. The output data has an internal
latency of five clock cycles. Figure 3 also determines
the relationship between the input clock parameters
and the valid output data on channels A and B.
All digital outputs, D0A–D7A (channel A) and D0B–D7B
(channel B), are TTL/CMOS-logic compatible. There is a
five-clock-cycle latency between any particular sample
and its corresponding output data. The output
coding can either be straight offset binary or two’s com-
plement (Table 1) controlled by a single pin (T/B). Pull
T/B low to select offset binary and high to activate two’s
complement output coding. The capacitive load on the
digital outputs D0A–D7A and D0B–D7B should be kept
as low as possible (<15pF), to avoid large digital cur-
rents that could feed back into the analog portion of the
MAX1198, thereby degrading its dynamic performance.
Using buffers on the digital outputs of the ADCs can fur-
ther isolate the digital outputs from heavy capacitive
loads. To further improve the dynamic performance of
the MAX1198, small-series resistors (e.g., 100Ω) may
be added to the digital output paths close to the
MAX1198.
Figure 4 displays the timing relationship between out-
put enable and data output valid, as well as power-
down/wakeup and data output valid.
14
Digital Output Data (D0A/B–D7A/B), Output
D7A–D0A
D7B–D0B
OUTPUT
OUTPUT
______________________________________________________________________________________
OE
Data Format Selection (T/B), Output
DD
HIGH-Z
HIGH-Z
/2. Clock inputs with a duty cycle other
System Timing Requirements
t
ENABLE
VALID DATA
VALID DATA
t
DISABLE
Enable ( OE )
HIGH-Z
HIGH-Z
Table 1. MAX1198 Output Codes For
Differential Inputs
*V
The MAX1198 offers two power-save modes—sleep
mode (SLEEP) and full power-down (PD) mode. In
sleep mode (SLEEP = 1), only the reference bias circuit
is active (both ADCs are disabled), and current con-
sumption is reduced to 3.2mA.
To enter full power-down mode, pull PD high. With OE
simultaneously low, all outputs are latched at the last
value prior to power-down. Pulling OE high forces the
digital outputs into a high-impedance state.
Figure 5 depicts a typical application circuit containing
two single-ended-to-differential converters. The internal
reference provides a V
shifting purposes. The input is buffered and then split
to a voltage follower and inverter. One lowpass filter per
amplifier suppresses some of the wideband noise
associated with high-speed op amps. The user can
select the R
formance, to suit a particular application. For the appli-
cation in Figure 5, a R
capacitive load to prevent ringing and oscillation. The
22pF C
An RF transformer (Figure 6) provides an excellent
solution to convert a single-ended source signal to a
fully differential signal, required by the MAX1198 for
optimum performance. Connecting the center tap of the
transformer to COM provides a V
the input. Although a 1:1 transformer is shown, a step-
up transformer can be selected to reduce the drive
-V
-V
V
D IFF ER EN T IAL
REF
-V
V
REF
REF
REF
VO LT A G E*
REF
REF
IN PU T
= V
x 255/256
x 255/256
x 256/256
IN
x 1/256
0
x 1/256
REFP
capacitor acts as a small filter capacitor.
ISO
- V
REFN
Applications Information
and C
D IFF ER EN T IAL
Power-Down and Sleep Modes
Bipolar Zero
+Full Scale
-Full Scale
-Full Scale
Using Transformer Coupling
+ 1LSB
- 1LSB
+1LSB
IN PU T
-1LSB
IN
ISO
values to optimize the filter per-
DD
of 50Ω is placed before the
/2 output voltage for level-
ST RA IG HT
1111 1111
1000 0001
1000 0000
0111 1111
0000 0001
0000 0000
O F FSET
B INA R Y
T/B = 0
DD
/2 DC level shift to
C O M PL EM EN T
0111 1111
0000 0001
0000 0000
1111 1111
1000 0001
1000 0000
T/B = 1
T WO’S