IS43R32400D-5BL ISSI, Integrated Silicon Solution Inc, IS43R32400D-5BL Datasheet - Page 5

• Manufacturer Part Number: IS43R32400D-5BL
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: DDR SDRAMr

Specifications of IS43R32400D-5BL

• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 700ps
• Maximum Clock Rate: 200MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Supply Current: 185mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

IS43R32400D, IS43R16800D
PIN FUNCTIONAL DESCRIPTIONS
Integrated Silicon Solution, Inc.
Rev. 00D
06/22/09
LDQS,UDDS
DQS0-DQS3
DQS for x16:
DM for x16;
DQ for x16:
DQ0-DQ15
DQ0-DQ31
RAS, CAS,
LDM, UDM
DM0-DM3
BA0, BA1
Symbol
CK, CK
for x32;
for x32:
for x32:
A [n:0]
VDDQ
VSSQ
VREF
VDD
CKE
VSS
WE
CS
NC
Supply SSTL_2 reference voltage
Supply I/O Power Supply
Supply I/O Ground
Supply Power Supply
Supply Ground
Type
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
--
Description
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Input and output data is
referenced to the crossing of CK and CK (both directions of crossing). Internal clock signals are
derived from CK/ CK.
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWERDOWN (row
ACTIVE in any bank). CKE is synchronous for all functions except for SELF REFRESH EXIT,
which is achieved asynchronously. Input buffers, excluding CK, CK and CKE, are disabled during
power-down and self refresh mode which are contrived for low standby power consumption.
Chip Select: CS enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS is registered HIGH. CS provides for external bank
selection on systems with multiple banks. CS is considered part of the command code.
WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being
entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges
of DQS. Although DM pins are input-only, the DM loading matches the DQ and DQS loading.
For x16 devices, LDM corresponds to the data on DQ0-DQ7, UDM corresponds to the data on
DQ8-DQ15.
For x32 devices, DM0 corresponds to the data on DQ0-DQ7, DM1 corresponds to the data on
DQ8-DQ15, DM2 corresponds to the data on DQ16-DQ23, and DM3 corresponds to the data on
DQ24-DQ31.
Input Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
Address Inputs: provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ / WRITE commands, to select one location out of the
memory array in the respective bank. The address inputs also provide the opcode during a
MODE REGISTER SET command.
Data Bus: Input / Output
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered
with write data. Used to capture write data.
For x16 device, LDQS corresponds to the data on DQ0-DQ7, UDQS corresponds to the data on
DQ8-DQ15.
For x32 device, DQS0 corresponds to the data on DQ0-DQ7, DQS1 corresponds to the data on
DQ8-DQ15, DQS2 corresponds to the data on DQ16-DQ23, and DQS3 corresponds to the data
on DQ24-DQ31.
No Connect: Should be left unconnected.
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