IS43R32400D-5BL ISSI, Integrated Silicon Solution Inc, IS43R32400D-5BL Datasheet
IS43R32400D-5BL
Specifications of IS43R32400D-5BL
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IS43R32400D-5BL Summary of contents
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... IS43R16800D, IS43R32400D 4Mx32, 8Mx16 128Mb DDR SDRAM FEATURES • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data used in capturing data at the receiver • DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs • ...
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... IS43R32400D, IS43R16800D FUNCTIONAL BLOCK DIAGRAM ( CLK COMMAND CLK DECODER CKE & CS CLOCK RAS GENERATOR CAS WE MODE REGISTERS A11 14 A10 ROW BA0 ADDRESS BA1 LATCH 12 14 COLUMN ADDRESS LATCH 8 BURST COUNTER COLUMN ADDRESS BUFFER 2 32) x REFRESH CONTROLLER SELF REFRESH CONTROLLER REFRESH COUNTER ...
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... IS43R32400D, IS43R16800D PIN CONFIGURATION Package Code B: 60-ball FBGA (top view) (8mm x 13mm Body, 0.8mm Ball Pitch) Top View (Balls seen through the Package) : Ball Existing : Depopulated Ball Top View(See the balls through the Package BGA Package Ball Pattern Top View PIN DESCRIPTION: for x16 ...
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... IS43R32400D, IS43R16800D PIN CONFIGURATION Package Code B: 144-ball FBGA (top view) (12mm x 12mm Body, 0.8mm Ball Pitch) Top View (Balls seen through the package DQS0 DM0 B DQ4 VDDQ C DQ6 DQ5 D DQ7 VDDQ E DQ17 DQ16 F DQ18 DQ19 G DM2 DQS2 H DQ20 DQ21 J DQ23 DQ22 ...
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... IS43R32400D, IS43R16800D PIN FUNCTIONAL DESCRIPTIONS Symbol Type Description CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Input and output data is referenced to the crossing of CK and CK (both directions of crossing). Internal clock signals are derived from CK/ CK ...
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... IS43R32400D, IS43R16800D Power Applied Power On Precharge PREALL MRS EMRS Write Write A PREALL = Precharge All Banks CKEL = Enter Power Down MRS = Mode Register Set CKEH = Exit Power Down EMRS = Extended Mode Register Set ACT = Active 6 SIMPLIFIED STATE DIAGRAM REFS REFSX MRS REFA ...
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... IS43R32400D, IS43R16800D FUNCTIONAL DESCRIPTION The DDR SDRAM is a high speed CMOS, dynamic random-access memory internally configured as a quad-bank DRAM. The 128 Mb devices contains: 134,217,728 bits. The DDR SDRAM uses double data rate architecture to achieve high speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins ...
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... IS43R32400D, IS43R16800D Initialization Waveform Sequence Notes VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch--up tMRD is required before any command can be applied, and 200 cycles of CK are required before any executable command can be applied The two Auto Refresh commands may be moved to follow the first MRS but precede the second PRECHARGE ALL command ...
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... IS43R32400D, IS43R16800D MODE REGISTER (MR) DEFINITION The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the definition of a burst length, a burst type, and a CAS latency. The Mode Register is programmed via the MODE REGISTER SET command (with BA0=0 and BA1=0) and will retain the stored information until it is reprogrammed, the device goes into Deep Power-Down mode, or the device loses power ...
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... IS43R32400D, IS43R16800D BURST LENGTH Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being set and the burst order as in Burst Definition. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths locations are available for both the sequential and the interleaved burst types ...
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... IS43R32400D, IS43R16800D When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within the block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-An when the burst length is set to two, by A2-An when the burst length is set A3-An when the burst length is set to 8 and A4-An when the burst length is set to 16 (where An is the most significant column address bit for a given configuration) ...
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... IS43R32400D, IS43R16800D 12 CAS LATENCIES Integrated Silicon Solution, Inc. Rev. 00D 06/22/09 ...
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... IS43R32400D, IS43R16800D EXTENDED MODE REGISTER (EMR) DEFINITION The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, and output drive strength selection. The Extended Mode Register is programmed via the MODE REGISTER SET command (with BA1=0 and BA0=1) and will retain the stored information until it is reprogrammed, or the device loses power ...
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... IS43R32400D, IS43R16800D Absolute Maximum Rating Parameter Voltage on any pin relative to VSS Voltage on VDD & VDDQ supply relative to VSS Storage temperature Power dissipation Short circuit current Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. ...
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... IS43R32400D, IS43R16800D CAPACITANCE CHARACTERISTICS = 2.5V ± 0.2V (-5, -6 ddq Symbol Parameter CI(A) Input Capacitance, address pin CI(C) Input Capacitance, control pin CI(K) Input Capacitance, CLK pin CI/O I/O Capacitance, I/O, DQS, DM pin Integrated Silicon Solution, Inc. Rev. 00D 06/22/09 = 2.5V ± 0.125V (-4), Vss = VssQ = 0V, unless otherwise noted) ...
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... IS43R32400D, IS43R16800D IDD Specification Parameters and Test Conditions: x16 = 2.5V ± 0.2V (-5, -6 ddq dd Symbol Parameter/ Test Condition IDD0 Operating current for one bank active-precharge; tRC = tRC(min); tCK = tCK(min); DQ, DM and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles ...
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... IS43R32400D, IS43R16800D IDD Specification Parameters and Test Conditions: x32 = 2.5V ± 0.2V (-5, -6 ddq dd Symbol Parameter/ Test Condition IDD0 Operating current for one bank active-precharge; tRC = tRC(min); tCK = tCK(min); DQ, DM and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles ...
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... IS43R32400D, IS43R16800D AC TIMING REQUIREMENTS Absolute Specifications (VDD, VDDQ = 2.5V ± 0.125V@-4) PARAMETER DQ output access time for CLK,/CLK DQS output access time for CLK,/CLK CLK high-level width CLK low-level width CLK half period CLK cycle time CL=4 CL=3 CL=2.5 CL=2 ...
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... IS43R32400D, IS43R16800D AC TIMING REQUIREMENTS Absolute Specifications (VDD, VDDQ = 2.5V ± 0.125V@-4) PARAMETER ACTIVE to ACTIVE/Auto Refresh command period Auto Refresh to Active/Auto ACTIVE to READ or WRITE delay PRECHARGE command period Active to Autoprecharge Delay ACTIVE bank A to ACTIVE bank B command Write recovery time Auto Precharge write recovery + precharge time ...
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... IS43R32400D, IS43R16800D AC TIMING REQUIREMENTS Absolute Specifications (VDD, VDDQ = 2.5V ± 0.2V@-5, -6) PARAMETER DQ output access time for CLK,/CLK DQS output access time for CLK,/CLK CLK high-level width CLK low-level width CLK half period CLK cycle time CL=4 CL=3 CL=2.5 ...
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... IS43R32400D, IS43R16800D AC TIMING REQUIREMENTS Absolute Specifications (VDD, VDDQ = 2.5V ± 0.2 V@-5, -6) PARAMETER ACTIVE to ACTIVE/Auto Refresh command period Auto Refresh to Active/Auto ACTIVE to READ or WRITE delay PRECHARGE command period Active to Autoprecharge Delay ACTIVE bank A to ACTIVE bank B command Write recovery time Auto Precharge write recovery + precharge ...
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... IS43R32400D, IS43R16800D Output Load Condition REF Ω OUT Ω Zo=50 30pF 22 DQS V REF V REF DQ V REF OutputTiming Measurement Reference Point Integrated Silicon Solution, Inc. Rev. 00D 06/22/09 ...
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... IS43R32400D, IS43R16800D Notes 1. All voltages referenced to Vss. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified timing and IDD tests may use a VIL to VIH swing 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK//CK), and parameter specifications are guaranteed for the specified AC input levels un- der normal use conditions ...
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... IS43R32400D, IS43R16800D OUTPUT SLEW RATE CHARACTERISTICS (x16) Slew Rate Characteristic Typical Range (V/ns) Pullup Slew Rate 1.2-2.5 Pulldown Slew Rate 1.2-2.5 OUTPUT SLEW RATE CHARACTERISTICS (x32) Slew Rate Characteristic Typical Range (V/ns) Pullup Slew Rate 1.2-2.5 Pulldown Slew Rate 1.2-2.5 24 Min ...
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... IS43R32400D, IS43R16800D DRIVER CHARACTERISTICS DDR SDRAM output driver characteristics are defined for full and weak drive strength operation as selected in the Extended Mode Register bit A1. The table below shows the data in a tabular format suitable for input into simulation tools. The following figures show the driver strength characteristics graphically. ...
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... IS43R32400D, IS43R16800D Pullup characteristics for Full Strength Output Driver 0 0 0.5 --50 --100 --150 --200 --250 Pulldown characteristics for Full Strength Output Driver 160 140 120 100 0 1.5 Nominal Low VDDQ to VOUT (V) Nominal Low Nominal High 1 1.5 2 VOUT to VSSQ (V) 2 2.5 3 Nominal High ...
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... IS43R32400D, IS43R16800D Weak Driver Characteristics Pull Down Current (mA) Voltage Nominal Nominal (V) Low High 0.1 3.4 3.8 0.2 6.9 7.6 0.3 10.3 11.4 0.4 13.6 15.1 0.5 16.9 18.7 0.6 19.6 22.1 0.7 22.3 25 0.8 24.7 28.2 0.9 26.9 31 34.1 1.1 30.6 36 ...
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... IS43R32400D, IS43R16800D Pullup Characteristics for Weak Output Driver 0 0 0.5 --10 --20 --30 --40 --50 --60 --70 --80 Nominal Low Nominal High - -90 Pulldown Characteristics for Weak Output Driver 0 1.5 2 Minimum Maximum VDDQ to VOUT (V) Nominal Low Nominal High 1 1.5 2 VOUT to VSSQ (V) 2.5 3 Minimum Maximum 2.5 3 Integrated Silicon Solution, Inc. ...
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... IS43R32400D, IS43R16800D COMMANDS TRUTH TABLES All commands (address and control signals) are registered on the positive edge of clock (crossing of CK going high and CK going low). Truth Table shows basic timing parameters for all commands. Truth Tables for Commands provide a quick reference of available commands. Table "Current State" provides the current state / next state information ...
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... IS43R32400D, IS43R16800D TRUTH TABLE - CKE CKEn-1 CKEn CURRENT STATE COMMANDn L L Power-Down L L Self Refresh L H Power-Down L H Self Refresh H L All Banks Idle H L Bank(s) Active H L All Banks Idle H H NOTE: 1. CKEn is the logic state of CKE at clock edge n; CKEn--1 was the state of CKE at the previous clock edge. ...
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... IS43R32400D, IS43R16800D TRUTH TABLE - Current State Bank n -- Command to Bank n CURRENT CS RAS CAS STATE Any Idle Row Active Read (Auto Precharge Disabled Write (Auto- Precharge Disabled NOTE: 1. This table applies when CKEn--1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSNR or tXSRD has been met (if the previous state was self refresh) ...
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... IS43R32400D, IS43R16800D TRUTH TABLE - CURRENT STATE BANK n - COMMAND TO BANK m CURRENT RAS CAS WE COMMAND/ACTION CS STATE Any Idle Row Activating, Active Precharging Read (Auto Precharge Disabled Write (Auto Precharge Disabled Read (With Auto- Precharge Write (With Auto-Precharge NOTE: 1. This table applies when CKEn--1 was HIGH and CKEn is HIGH and after tXSNR or tXSRD has been met (if the previous state was self refresh) ...
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... IS43R32400D, IS43R16800D 3b. For devices which do support the optional “concurrent auto precharge” feature, a read with auto precharge enabled write with auto precharge enabled, may be followed by any command to the other banks, as long as that command does not interrupt the read or write data transfer, and all other related limitations apply (e.g., contention between READ data and WRITE data must be avoided ...
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... IS43R32400D, IS43R16800D OPERATION DESELECT The DESELECT function (CS = High) prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION The NO OPERATION (NOP) command is used to perform a NOP to a DDR SDRAM that is selected (CS = Low). This prevents unwanted commands from being registered during idle or wait states ...
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... IS43R32400D, IS43R16800D ACTIVE Before any READ or WRITE commands can be issued to a bank in the DDR SDRAM, a row in that bank must be opened. This is accomplished by the ACTIVE command: BA0 and BA1 select the bank, and the address inputs select the row to be activated. More than one bank can be active at anytime. ...
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... IS43R32400D, IS43R16800D READ The READ command is used to initiate a burst read access to an active row, with a burst length as set in the Mode Register. BA0 and BA1 select the bank, and the address inputs select the starting column location. The value of A10 (or A8 for x32) determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed will be precharged at the end of the read burst ...
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... IS43R32400D, IS43R16800D READ to READ Data from a read burst may be concatenated or truncated by a subsequent READ command. The first data from the new burst follows either the last element of a completed burst or the last desired element of a longer burst that is being truncated. The new READ command should be issued X cycles after the first READ command, where X equals the number of desired data-out element pairs (pairs are required by the 2n prefetch architecture) ...
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... IS43R32400D, IS43R16800D Notes Data Out from column n Burst Length = 4 3 subsequent elements of Data Out appear in the programmed order following Read Burst Showing CAS Latency Integrated Silicon Solution, Inc. Rev. 00D 06/22/09 ...
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... IS43R32400D, IS43R16800D Notes ( Data Out from column n (or column b) Burst Length = (if 4, the bursts are concatenated the second burst interrupts the first) 3 subsequent elements of Data Out appear in the programmed order following (or 7) subsequent elements of Data Out appear in the programmed order following DO b Read commands shown must be to the same device Integrated Silicon Solution, Inc ...
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... IS43R32400D, IS43R16800D Notes ( Data Out from column n (or column b) Burst Length = 4 3 subsequent elements of Data Out appear in the programmed order following DO n (and following Non-Consecutive Read Bursts Integrated Silicon Solution, Inc. Rev. 00D 06/22/09 ...
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... IS43R32400D, IS43R16800D Notes etc. = Data Out from column n, etc. n’ , etc. = the next Data Out following DO n, etc. according to the programmed burst order Burst Length = cases shown. If burst the burst is interrupted, Reads are to active rows in any banks Integrated Silicon Solution, Inc. ...
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... IS43R32400D, IS43R16800D Notes Data Out from column n Cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of Data Out appear in the programmed order following Terminating a Read Burst Integrated Silicon Solution, Inc. Rev. 00D 06/22/09 ...
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... IS43R32400D, IS43R16800D Notes ( Data Out from column n (or column b) Burst Length = 4 in the cases shown (applies for bursts well; if burst length is 2, the BST command shown can be NOP) 1 subsequent element of Data Out appears in the programmed order following DO n Data In elements are applied following the programmed order Integrated Silicon Solution, Inc ...
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... IS43R32400D, IS43R16800D Notes Data Out from column n Cases shown are either uninterrupted bursts interrupted bursts subsequent elements of Data Out appear in the programmed order following DO n Precharge may be applied at (BL/2) tCK after the READ command. Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks. ...
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... IS43R32400D, IS43R16800D WRITE The WRITE command is used to initiate a burst write access to an active row, with a burst length as set in the Mode Register. BA0 and BA1 select the bank, and the address inputs select the starting column location. The value of A10 (or A8 for x32) determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed will be precharged at the end of the write burst ...
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... IS43R32400D, IS43R16800D During Write bursts, the first valid data-in element will be registered on the first rising edge of DQS following the WRITE command, and the subsequent data elements will be registered on successive edges of DQS. The Low state of DQS between the WRITE command and the first rising edge is called the write preamble, and the Low state on DQS following the last data-in element is called the write postamble ...
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... IS43R32400D, IS43R16800D WRITE to PRECHARGE: Data for any WRITE burst may be followed by a subsequent PRECHARGE command to the same bank (provided Auto Precharge was not activated). To follow a WRITE without truncating the WRITE burst, tWR should be met. Data for any WRITE burst may be truncated by a subsequent PRECHARGE command. ...
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... IS43R32400D, IS43R16800D Notes etc. = Data In for column b, etc. Three subsequent elements of Data In are applied in the programmed order following DI b Three subsequent elements of Data In are applied in the programmed order following DI n Noninterrupted bursts of 4 are shown Each WRITE command may be to any bank and may be to the same or different devices ...
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... IS43R32400D, IS43R16800D Notes etc. = Data In for column b, etc. b’, etc. = the next Data In following DI b, etc. according to the programmed burst order. Programmed Burst Length = cases shown. If burst the burst would be truncated. Each WRITE command may be to any bank and may be to the same or different devices. ...
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... IS43R32400D, IS43R16800D Notes Data In for column b Three subsequent elements of Data In are applied in the programmed order following non-interrupted burst shown tWTR is referenced from the first positive CK edge after the last Data In pair tWTR = 2tCK for optional CL = 1.5 (otherwise tWTR = 1tCK LOW with the WRITE command (AUTO PRECHARGE is disabled) ...
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... IS43R32400D, IS43R16800D Notes Data In for column b An interrupted burst shown, 4 data elements are written Three subsequent elements of Data In are applied in the programmed order following DI b tWTR is referenced from the first positive CK edge after the last Data In pair tWTR = 2tCK for optional CL = 1.5 (otherwise tWTR = 1tCK) ...
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... IS43R32400D, IS43R16800D Notes Data In for column b Three subsequent elements of Data In are applied in the programmed order following non-interrupted burst shown tWR is referenced from the first positive CK edge after the last Data In pair AP is LOW with the WRITE command (AUTO PRECHARGE is disabled) 52 Non-Interrupting Write to Precharge Integrated Silicon Solution, Inc ...
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... IS43R32400D, IS43R16800D Notes Data In for column b An interrupted burst shown, 2 data elements are written tWR is referenced from the first positive CK edge after the last desired Data In pair AP is LOW with the WRITE command (AUTO PRECHARGE is disabled can be don’t care for programmed burst length for programmed burst length of 4, DQS becomes don’ ...
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... IS43R32400D, IS43R16800D PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10(x16) or A8(x32) determines whether one or all banks are to be precharged. In case where only one bank precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “ ...
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... IS43R32400D, IS43R16800D REFRESH REQUIREMENTS DDR SDRAM devices require a refresh of all rows in any 64ms(x16) or 32ms(x32). Each refresh is generated in one of two ways explicit AUTO REFRESH command internally timed event in SELF REFRESH mode. Dividing the number of device rows into the rolling 64ms or 32ms interval defines the average refresh interval (tREFI), which is a guideline to controllers for distributed refresh timing ...
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... IS43R32400D, IS43R16800D SELF REFRESH The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the Self Refresh mode, the DDR SDRAM retains data without external clocking. The DDR SDRAM device has a built-in timer to accommodate Self Refresh operation. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is LOW. Input signals except CKE are “ ...
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... IS43R32400D, IS43R16800D Notes Device must be in the ”All banks idle” state prior to entering Self Refresh mode ** = tXSNR is required before any non--READ command can be applied, and tXSRD (200 cycles of CK) is required before a READ command can be applied. Integrated Silicon Solution, Inc. ...
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... IS43R32400D, IS43R16800D POWER-DOWN Power-down is entered when CKE is registered Low (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. ...
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... IS43R32400D, IS43R16800D Input Clock Frequency Change during Precharge Power Down The DDR SDRAM input clock frequency can be changed under following condition: DDR SDRAM must be in precharged power down mode with CKE at logic LOW level. After a minimum of 2 clocks after CKE goes LOW, the clock frequency may change to any frequency between minimum and maximum operating frequency specified for the particular speed grade ...
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... MHz 6 IS43R32400D-6BL Industrial Range: -40°C to +85°C Frequency Speed (ns) Order Part No. 250 MHz 4 IS43R32400D-4BLI 200 MHz 5 IS43R32400D-5BLI 166 MHz 6 IS43R32400D-6BLI 60 Package 60-ball FBGA, Lead-free 60-ball FBGA, Lead-free 60-ball FBGA, Lead-free Package 60-ball FBGA, Lead-free 60-ball FBGA, Lead-free 60-ball FBGA, Lead-free ...
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... IS43R32400D, IS43R16800D Mini Ball Grid Array Package Code: B (60-Ball) 8mm x 13mm Integrated Silicon Solution, Inc. Rev. 00D 06/22/09 61 ...
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... IS43R32400D, IS43R16800D 62 Integrated Silicon Solution, Inc. Rev. 00D 06/22/09 ...