IS43R32400D-5BL ISSI, Integrated Silicon Solution Inc, IS43R32400D-5BL Datasheet - Page 23

• Manufacturer Part Number: IS43R32400D-5BL
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: DDR SDRAMr

Specifications of IS43R32400D-5BL

• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 700ps
• Maximum Clock Rate: 200MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Supply Current: 185mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

IS43R32400D, IS43R16800D
Integrated Silicon Solution, Inc.
Rev. 00D
06/22/09
Notes
1. All voltages referenced to Vss.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage
3. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to
4. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver will effectively switch as a
5. VREF is expected to be equal to 0.5*VddQ of the transmitting device, and to track variations in the DC level of the same.
6. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
7. VID is the magnitude of the difference between the input level on CLK and the input level on /CLK.
8. The value of VIX is expected to equal 0.5*VddQ of the transmitting device and must track variations in the DC level of the
9. Enables on-chip refresh and address counters.
10. IDD specifications are tested after the device is properly initialized.
11. This parameter is sampled. VddQ = 2.5V+0.2V, Vdd = 2.5V + 0.2V , f = 100 MHz, Ta = 25oC, VOUT(DC) = VddQ/2,
12. The CLK//CLK input reference level (for timing referenced to CLK//CLK) is the point at which CLK and /CLK cross; the input
13. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE< 0.3VddQ
14. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not refer-
15. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but
16. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CLK
17. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
18. tXPRD should be 200 tCLK in the condition of the unstable CLK operation during the power down mode.
19. For command/address and CK & /CK slew rate > 1.0V/ns.
20. Min (tCL,tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device.
levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
VREF (or to the crossing point for CK//CK), and parameter specifications are guaranteed for the specified AC input levels un-
der normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and VIH(AC).
result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above
(below) the DC input LOW (HIGH) level.
Peak-to-peak noise on VREF may not exceed +2% of the DC value.
VREF, and must track variations in the DC level of VREF.
same.
VOUT(PEAK TO PEAK) = 25mV. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to
facilitate trace matching at the board level).
reference level for signals other than CLK//CLK, is VREF.
is recognized as LOW.
enced to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving (LZ).
system performance (bus turnaround) will degrade accordingly.
edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. When no writes
were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous write was in prog-
ress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
Timing patterns:
tCK = min, tRRD = 2*tCK, BL=4, tRCD = 3*tCK, Read with Autoprecharge
Read:A0 N A1 R0 A2 R1 N R3 A0 N A1 R0 – repeat the same timing with random address changing
*100% of data changing at every burst
Legend: A = Activate, R = Read, P = Precharge, N = NOP
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