IS43R32400D-5BL ISSI, Integrated Silicon Solution Inc, IS43R32400D-5BL Datasheet - Page 29

• Manufacturer Part Number: IS43R32400D-5BL
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: DDR SDRAMr

Specifications of IS43R32400D-5BL

• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 700ps
• Maximum Clock Rate: 200MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Supply Current: 185mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

IS43R32400D, IS43R16800D
COMMANDS TRUTH TABLES
All commands (address and control signals) are registered on the positive edge of clock (crossing of CK going high
and CK going low). Truth Table shows basic timing parameters for all commands.
Truth Tables for Commands provide a quick reference of available commands. Table "Current State" provides the
current state / next state information. This is followed by a detailed description of each command.
TRUTH TABLE - Commands
TRUTH TABLE - DM Operations
Integrated Silicon Solution, Inc.
Rev. 00D
06/22/09
NAME (Function)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO refresh or Self Refresh (Enter self refresh mode)
MODE REGISTER SET
NAME (Function)
Write Enable
Write Inhibit
NOTE:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. BA0--BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0
3. BA0--BA1 provide bank address and A0--An provide row address.
4. BA0--BA1 provide bank address; A0--Ai provide column address; AP HIGH enables the auto precharge feature (nonpersis-
5. AP LOW: BA0--BA1 determine which bank is precharged. AP HIGH: all banks are precharged and BA0--BA1 are ”Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are ”Don’t Care” except for CKE.
8. Applies only to read bursts with autoprecharge disabled; this command is undefined (and should not be used) for read bursts
9. DESELECT and NOP are functionally interchangeable.
10. Used to mask write data, provided coincident with the corresponding data.
11. Operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM
12. VREF must be maintained during Self Refresh operation.
selects Extended Mode Register; other combinations of BA0--BA1 are reserved; A0--An provide the op--code to be written to
the selected Mode Register.
tent), AP LOW disables the auto precharge feature.
with autoprecharge enabled, and for write bursts.
must be powered down and then restarted through the specified initialization sequence before normal operation can continue.
DM
H
L
Valid
DQs
X
NOTES
10
10
CS
H
L
L
L
L
L
L
L
L
RAS CAS
X
H
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
WE
X
H
H
H
H
L
L
L
L
Bank/Row 3
Bank/Col
Bank/Col
Op-Code
ADDR
Code
X
X
X
X
NOTES
9
9
4
4
8
5
6, 7, 12
2
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