CY7C65113-SXC Cypress Semiconductor Corp, CY7C65113-SXC Datasheet - Page 21

• Manufacturer Part Number: CY7C65113-SXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113-SXC

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: SOIC
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Document #: 38-08002 Rev. *D
12.0
The I2C-compatible block provides a versatile two-wire communication with external devices, supporting master, slave, and
multi-master modes of operation. The I2C-compatible block functions by handling the low-level signaling in hardware, and issuing
interrupts as needed to allow firmware to take appropriate action during transactions. While waiting for firmware response, the
hardware keeps the I2C-compatible bus idle if necessary.
The I2C-compatible block generates an interrupt to the microcontroller at the end of each received or transmitted byte, when a
stop bit is detected by the slave when in receive mode, or when arbitration is lost. Details of the interrupt responses are given in
Section 14.8.
The I2C-compatible interface consists of two registers, an I
(Figure 12-2). The I
Register should only be monitored after the I
read misleading bit status if a transaction is underway.
The I
selection is determined by settings in the I
enabled by setting the I
corresponding GPIO port is placed in Open Drain mode, regardless of the settings of the GPIO Configuration Register. In Open
Drain mode, the GPIO pin outputs LOW if the pin’s Data Register is ‘0’, and the pin is in Hi-Z mode if the pin’s Data Register is
‘1’. The electrical characteristics of the I
mA @ V
All control of the I
Bits [7..0]: I
The I
Table 12-1. I
I2C Data
Bit #
Bit Name
Read/Write
Reset
I
Bit #
Bit Name
Read/Write
Reset
2
C Status and Control
Bit
0
1
2
3
4
5
2
2
Contains the 8-bit data on the I
C Status and Control register bits are defined in Table 12-1, with a more detailed description following.
C clock (SCL) is connected to bit 0 of GPIO port 1, and the I
OL
I2C-compatible Controller
I
Received Stop
ARB Lost/Restart Reads 1 to indicate master has lost arbitration. Reads 0 otherwise.
Addr
ACK
Xmit Mode
2
= 2.0V for port 1.
2
C Enable
C Data
2
C Status and Control Register Bit Definitions
MSTR Mode Continue/Bu
I
2
Name
2
C Data 7
C clock (SCL) and data (SDA) lines is performed by the I
R/W
R/W
2
X
C Data Register is implemented as separate read and write registers. Generally, the I
7
7
0
2
C Enable bit of the I
When set to ‘1’, the I
normally.
Reads 1 only in slave receive mode, when I
last transaction).
Write to 1 in master mode to perform a restart sequence (also set Continue bit).
Reads 1 during first byte after start/restart in slave mode, or if master loses arbitration.
Reads 0 otherwise. This bit should always be written as 0.
In receive mode, write 1 to generate ACK, 0 for no ACK.
In transmit mode, reads 1 if ACK was received, 0 if no ACK received.
Write to 1 for transmit mode, 0 for receive mode.
I
2
C Data 6
R/W
R/W
sy
X
6
6
0
2
C Bus.
2
Figure 12-2. I
C-compatible interface is the same as that of GPIO port 1. Note that the I
2
C Port Configuration Register (Section 11.0). Once the I
2
Xmit Mode
I
C interrupt, as all bits are valid at that time. Polling this register at other times could
2
C Data 5
2
R/W
R/W
Figure 12-1. I
C Status and Control Register (bit 0, Figure 12-2), the two LSB ([1:0]) of the
X
5
5
0
2
C-compatible function is enabled. When cleared, I
2
C Status and Control Register
2
I
C Data Register (Figure 12-1) and an I
2
C Data 4
ACK
R/W
R/W
2
C Data Register
X
4
4
0
2
C SDA data is connected to bit 1 GPIO port 1. The port
Description
I
2
2
C Stop bit detected (unless firmware did not ACK the
C Data 3
Addr
2
R/W
R/W
C-compatible block.
3
X
3
0
Lost/Restart
I
2
C Data 2
ARB
R/W
R/W
X
2
2
0
2
C Status and Control Register
2
C-compatible functionality is
I
Received
2
2
C Data 1
C GPIO pins operate
Stop
R/W
R/W
CY7C65113C
X
2
1
1
0
C Status and Control
Address 0x29
Address 0x28
Page 21 of 49
OL
I
I
2
2
C Enable
C Data 0
(max) is 2
R/W
R/W
X
0
0
0