CY7C65113-SXC Cypress Semiconductor Corp, CY7C65113-SXC Datasheet - Page 17

• Manufacturer Part Number: CY7C65113-SXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113-SXC

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: SOIC
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Document #: 38-08002 Rev. *D
9.0
There are 11 GPIO pins (P0[7:0] and P1[2:0]) for the hardware interface. Each port can be configured as inputs with internal
pull-ups, open drain outputs, or traditional CMOS outputs. The data for each GPIO port is accessible through the data registers.
Port data registers are shown in Figure 9-2 through Figure 9-3, and are set to 1 on reset.
.
Special care should be taken with any unused GPIO data bits. An unused GPIO data bit, either a pin on the chip or a port bit that
is not bonded on a particular package, must not be left floating when the device enters the suspend state. If a GPIO data bit is
left floating, the leakage current caused by the floating bit may violate the suspend current limitation specified by the USB
Specifications. If a ‘1’ is written to the unused data bit and the port is configured with open drain outputs, the unused data bit
remains in an indeterminate state. Therefore, if an unused port bit is programmed in open-drain mode, it must be written with a ‘0.’
A read from a GPIO port always returns the present state of the voltage at the pin, independent of the settings in the Port Data
Registers. During reset, all of the GPIO pins are set to a high-impedance input state. Writing a ‘0’ to a GPIO pin drives the pin
LOW. In this state, a ‘0’ is always read on that GPIO pin unless an external source overdrives the internal pull-down device.
Port 0 Data
Bit #
Bit Name
Read/Write
Reset
Port 1 Data
Bit #
Bit Name
Read/Write
Reset
General-purpose I/O Ports
P0.7
R/W
(Latch is Transparent)
7
1
-
-
-
-
Interrupt
Enable
Interrupt
Controller
Port Write
OE
Reg_Bit
Port Read
Internal
Data Bus
STRB
P0.6
R/W
GPIO
CFG
6
1
-
-
-
-
Figure 9-1. Block Diagram of a GPIO Pin
Data
In
Latch
Data
Interrupt
Latch
Data
Out
Latch
P0.5
R/W
5
1
-
-
-
-
Figure 9-2. Port 0 Data
Figure 9-3. Port1 Data
P0.4
mode
2-bits
R/W
4
1
-
-
-
-
Q3*
*Port 0,1: Low I
Q1
14 kΩ
P0.3
R/W
V
3
1
CC
-
-
-
-
Q2
sink
P0.2
P1.2
R/W
R/W
2
1
2
1
GPIO
PIN
P1.1
P0.1
R/W
R/W
CY7C65113C
1
1
1
1
Address 0x01
Address 0x00
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P1.0
P0.0
R/W
R/W
0
1
0
1