MT28C3214P2NFL-11 TET Micron Technology Inc, MT28C3214P2NFL-11 TET Datasheet - Page 15

• Manufacturer Part Number: MT28C3214P2NFL-11 TET
• Manufacturer: Micron Technology Inc

Specifications of MT28C3214P2NFL-11 TET

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

PROGRAMMING OPERATIONS
PROGRAM SETUP and ALTERNATE PROGRAM SETUP
(see Table 4).
40h command code on DQ0–DQ7), the WSM takes over
and correctly sequences the device to complete the
PROGRAM operation. The WRITE operation may be
monitored through the status register (see the Status
Register section). During this time, the CSM only re-
sponds to a PROGRAM SUSPEND command until the
PROGRAM operation has been completed, after which
time all commands to the CSM become valid again.
The PROGRAM operation can be suspended by issuing
a PROGRAM SUSPEND command (B0h). Once the WSM
reaches the suspend state, it allows the CSM to re-
spond only to READ ARRAY, READ STATUS REGISTER,
READ PROTECTION CONFIGURATION, READ QUERY,
PROGRAM SETUP, or PROGRAM RESUME. During the
PROGRAM SUSPEND operation, array data should be
read from an address other than the one being pro-
grammed. To resume the PROGRAM operation, a PRO-
GRAM RESUME command (D0h) must be issued to
cause the CSM to clear the suspend state previously
set (see Figure 4 for programming operation and Figure
5 for program suspend and program resume).
PROGRAM operation.
ERASE OPERATIONS
bits in an array block to “1s.” After BLOCK ERASE con-
firm is issued, the CSM responds only to an ERASE
SUSPEND command until the WSM completes its task.
within the address block to logic 1s. Erase is accom-
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02
MODE
Read (array, status registers,
device identification register, or
query)
Standby
Output Disable
Reset
Write
There are two CSM commands for programming:
After the desired command code is entered (10h or
Taking F_RP# to V
An ERASE operation must be used to initialize all
Block erasure inside the memory array sets all bits
IL
during programming aborts the
F_RP#
V
V
V
V
V
IH
IH
IH
IH
IL
Bus Operations
Table 7
F_CE#
15
V
V
V
V
256K x 16 SRAM COMBO MEMORY
X
IH
IH
IL
IL
plished only by blocks; data at single address locations
within the array cannot be erased individually. The
block to be erased is selected by using any valid ad-
dress within that block. Block erasure is initiated by a
command sequence to the CSM: BLOCK ERASE setup
(20h) followed by BLOCK ERASE CONFIRM (D0h) (see
Table 5). A two-command erase sequence protects
against accidental erasure of memory contents.
complete, the WSM automatically executes a sequence
of events to complete the block erasure. During this
sequence, the block is programmed with logic 0s, data
is verified, all bits in the block are erased, and finally
verification is performed to ensure that all bits are cor-
rectly erased. Monitoring of the ERASE operation is
possible through the status register (see the Status
Register section).
ERASE SUSPEND command (B0h) can be entered to
direct the WSM to suspend the ERASE operation. Once
the WSM has reached the suspend state, it allows the
CSM to respond only to the READ ARRAY, READ STA-
TUS REGISTER, READ QUERY, READ CHIP PROTEC-
TION CONFIGURATION, PROGRAM SETUP, PRO-
GRAM RESUME, ERASE RESUME and LOCK SETUP
(see the Block Locking section). During the ERASE SUS-
PEND operation, array data must be read from a block
other than the one being erased. To resume the ERASE
operation, an ERASE RESUME command (D0h) must
be issued to cause the CSM to clear the suspend state
previously set (see Figure 7). It is also possible that an
ERASE in any bank can be suspended and a WRITE to
another block in the same bank can be initiated. After
the completion of a WRITE, an ERASE can be resumed
by writing an ERASE RESUME command.
When the BLOCK ERASE CONFIRM command is
During the execution of an ERASE operation, the
F_OE#
V
V
X
X
X
IH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IL
2 MEG x 16 PAGE FLASH
F_WE#
V
V
X
X
X
IH
IL
ADDRESS DQ0–DQ15
X
X
X
X
X
©2002, Micron Technology, Inc.
High-Z
High-Z
High-Z
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