MT28C3214P2NFL-11 TET Micron Technology Inc, MT28C3214P2NFL-11 TET Datasheet - Page 11

• Manufacturer Part Number: MT28C3214P2NFL-11 TET
• Manufacturer: Micron Technology Inc

Specifications of MT28C3214P2NFL-11 TET

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

order I/O signals (DQ0–DQ7) need to be interpreted.
Address lines select the status register pertinent to the
selected memory partition.
edge of F_OE# or F_CE#, whichever occurs first. The
latest falling edge of either of these two signals up-
dates the latch within a given READ cycle. Latching the
data prevents errors from occurring if the register input
changes during a status register read.
WSM to the external microprocessor. During periods
when the WSM is active, the status register can be polled
to determine the WSM status. Table 8 defines the sta-
tus register bits.
PROGRAM/ERASE operation, the data appearing on
DQ0–DQ7 remains as status register data until a new
command is issued to the CSM. To return the device to
other modes of operation, a new command must be
issued to the CSM.
NOTE: 1. WA: Word address of memory location to be written, or read
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02
COMMAND
READ ARRAY
READ PROTECTION CONFIGURATION REGISTER
READ STATUS REGISTER
CLEAR STATUS REGISTER
READ QUERY
BLOCK ERASE SETUP
PROGRAM SETUP/ALTERNATE PROGRAM SETUP
PROGRAM/ERASE SUSPEND
PROGRAM/ERASE RESUME – ERASE CONFIRM
LOCK BLOCK
UNLOCK BLOCK
LOCK DOWN BLOCK
PROTECTION REGISTER PROGRAM
PROTECTION REGISTER LOCK
Register data is updated and latched on the rising
The status register provides the internal state of the
After monitoring the status register during a
10. LPA: Lock protection register address
11. PD: Protection register data
2. IA: Identification code address
3. BA: Address within the block
4. ID: Identification code data
5. SRD: Data read from the status register
6. QA: Query code address
7. QD: Query code data
8. WD: Data to be written at the location WA
9. PA: Protection register address
Command Definitions
OPERATION ADDRESS
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
Table 5
11
256K x 16 SRAM COMBO MEMORY
FIRST BUS CYCLE
COMMAND STATE MACHINE OPERATIONS
listed in Table 4. The 8-bit command code is input to
the device on DQ0–DQ7 (see Table 5 for command
definitions). During a PROGRAM or ERASE cycle, the
CSM informs the WSM that a PROGRAM or ERASE cycle
has been requested.
program sequences and the CSM responds to a PRO-
GRAM SUSPEND command only.
ERASE SUSPEND command only. When the WSM has
completed its task, the WSMS bit (SR7) is set to a logic
HIGH level and the CSM responds to the full command
set. The CSM stays in the current command state until
the microprocessor issues another command.
GRAM operation only when V
age range.
LPA
WA
WA
QA
BA
BA
BA
BA
BA
BA
BA
BA
PA
IA
The CSM decodes instructions for the commands
During a PROGRAM cycle, the WSM controls the
During an ERASE cycle, the CSM responds to an
The WSM successfully initiates an ERASE or PRO-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
40h/10h
DATA
2 MEG x 16 PAGE FLASH
FFh
90h
70h
50h
98h
20h
D0h
60h
60h
60h
C0h
C0h
B0h
OPERATION ADDRESS
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
READ
READ
READ
PP
SECOND BUS CYCLE
is within its correct volt-
LPA
WA
QA
BA
BA
BA
BA
BA
PA
IA
©2002, Micron Technology, Inc.
DATA
FFFDh
SRD
D0h
D0h
WD
01h
2Fh
QD
PD
ID