MT28C3214P2NFL-11 TET Micron Technology Inc, MT28C3214P2NFL-11 TET Datasheet - Page 12

• Manufacturer Part Number: MT28C3214P2NFL-11 TET
• Manufacturer: Micron Technology Inc

Specifications of MT28C3214P2NFL-11 TET

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02
CODE DEVICE MODE
10h
20h
40h
50h
60h
70h
90h
98h
B0h
C0h
Alt. Program Setup
Erase Setup
Program Setup
Clear Status
Register
Protection
Configuration
Setup
Read Status
Register
Read Protection
Configuration
Read Query
Program Suspend
Erase Suspend
Program Device
Protection Register
Lock Device
Protection register
BUS CYCLE
First
First
First
First
First
First
First
First
First
First
First
First
Command Descriptions
(continued on the next page)
Suspends the currently executing PROGRAM/ERASE operation. The
Operates the same as a PROGRAM SETUP command.
Prepares the CSM for an ERASE CONFIRM command. If the next
A two-cycle command: The first cycle prepares for a PROGRAM
The WSM can set the program status (SR4), and erase status (SR5) bits
Places the device into read status register mode. Reading the device
Puts the device into the read protection configuration mode so that
Puts the device into the read query mode so that reading the device
suspended by setting either the program suspend (SR2) or erase
Writes a specific code into the device protection register.
Locks the device protection register; data can no longer be changed.
command is not ERASE CONFIRM, the CSM sets both SR4 and SR5 of
the status register to a “1,” places the device into read status register
mode, and waits for another command.
operation, the second cycle latches addresses and data and initiates
the WSM to execute the program algorithm. The Flash outputs status
register data on the falling edge of F_OE# or F_CE#, whichever
occurs first.
this command clears those bits to “0.”
Prepares the CSM for changes to the block locking status. If the next
command is not BLOCK UNLOCK, BLOCK LOCK or BLOCK LOCK
DOWN, then the CSM sets both the program and erase status register
bits to indicate a command sequence error.
outputs the contents of the status register, regardless of the address
presented to the device. The device automatically enters this mode
after a PROGRAM or ERASE operation has been initiated.
reading the device outputs the manufacturer/device codes or block
lock status.
outputs common Flash interface information.
status register indicates when the operation has been successfully
suspend (SR6) and the WSMS bit (SR7) to a “1” (ready). The WSM
continues to idle in the suspend state, regardless of the state of all
input control pins except F_RP#, which immediately shuts down the
WSM and the remainder of the chip if F_RP# is driven to V
in the status register to “1,” but it cannot clear them to “0.” Issuing
Table 6
12
256K x 16 SRAM COMBO MEMORY
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
2 MEG x 16 PAGE FLASH
©2002, Micron Technology, Inc.
IL
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