TS86101G2BCGL E2V, TS86101G2BCGL Datasheet - Page 41

• Manufacturer Part Number: TS86101G2BCGL
• Manufacturer: E2V

Specifications of TS86101G2BCGL

• Lead Free Status / RoHS Status: Not Compliant

12.3
12.4
e2v semiconductors SAS 2009
CW_IN Master Clock Implementation
DSP Output Clock Implementation
In order to allow for any ECL/PECL/LVDS differential input levels, the CW_IN master input clock must be
AC-coupled through 10 nF capacitors (for information only) as shown in
Figure 12-8. CW_IN Master Input Clock Implementation in AC-coupled Differential Mode
Figure 12-9. CW_IN Master Input Clock Implementation in AC-coupled Singled-ended Mode
In order to make the DSP output clock compatible with standard differential levels such as LVDS and
PECL, the signals must be AC-coupled with 10 pF capacitors and used with pull-down resistors to
ensure appropriate biasing, as shown in the following three figures.
Three configurations are depicted:
• The load has a high impedance input buffer
• The load has a 100Ω differential buffer
• The DSP_CLK is sent to the load via a driver
Source
Driving
50Ω
+8 dBm (1.6 Vpp) max
-4 dBm (400 mVpp) to
Source
Driving
50Ω
AGND
+2 dBm (800 mVpp) max
-10 dBm (200 mVpp) to
+2 dBm (800 mVpp) max
-10 dBm (200 mVpp) to
50Ω
10 nF
10 nF
50Ω Lines
10 nF
10 nF
500Ω
50Ω lines
MUXDAC
VEEA
450Ω
500Ω
CW_IN_T
CW_IN_F
VEEA
450Ω
AGND
50Ω
MUXDAC
Figure
CW_IN_T
CW_IN_F
12-8.
AGND
CW Input
50Ω
Buffer
TS86101G2B
0992D–BDC–04/09
CW Input
Buffer
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