TS86101G2BCGL E2V, TS86101G2BCGL Datasheet - Page 22

• Manufacturer Part Number: TS86101G2BCGL
• Manufacturer: E2V

Specifications of TS86101G2BCGL

• Lead Free Status / RoHS Status: Not Compliant

5.3
22
Phase Relationship Between Data Ready and CW_IN Clock Input
0992D–BDC–04/09
Figure 5-3.
There is a forbidden time range in the phase relation between Data Ready and the CW_IN master clock.
This forbidden zone occurs when active rising edges of CW_IN and Data Ready do not comply with the
setup and hold times (see
second bank of master latches at the time when the first outputs of slave latches switch (acquisition of
next incoming data). Within this critical time range of 600 ps, data pattern throughput transmission errors
may occur.
To satisfy setup and hold times, the phase of the Data Ready input (D_CK_T to D_CK_F) can be
adjusted by choosing one of the 16 DSP clock shift positions (assuming that the DSP providing the data
and Data Ready signals to the MUXDAC is clocked by the MUXDAC DSP clock’s output signal).
Figure 5-4.
If the D_CK clock edge occurs within the forbidden zone, there is an ambiguity on the data to be trans-
ferred from the first to the second bank of latch (data N or data N + 1).
Data
Data
Clock
Tthold
Data to Data Clock Forbidden Area
Data Ready (D_CK) to CW_IN Master Clock Timing
Tsetup
allowed
CW_IN
D_CK
Figure 5-4 on page
1.2 ns max
forbidden
Forbidden area for rising edge
Thold
of D_CK = 600 ps max
Tsetup
allowed
22). Within this forbidden zone, the data is stored in the
3.1 ns
2.5 ns
forbidden
Thold
Tsetup
allowed
e2v semiconductors SAS 2009
1
2
forbidden
TS86101G2B
Thold
Tsetup