TS86101G2BCGL E2V, TS86101G2BCGL Datasheet - Page 21

• Manufacturer Part Number: TS86101G2BCGL
• Manufacturer: E2V

Specifications of TS86101G2BCGL

• Lead Free Status / RoHS Status: Not Compliant

5.2
e2v semiconductors SAS 2009
Registering the Input Data
Figure 5-1.
The 4 × 10-bit differential digital input data patterns (port A: [Ai_T, Ai_F], port B: [Bi_T, Bi_F], port C:
[Ci_T, Ci_F] and port D: [Di_T, Di_F]) are loaded in parallel into the first bank of master latches by the
rising edge (hold mode) of the differential Data Ready input (D_CK_T,D_CK_F).
Note:
The registered input data is latched in the second bank of master/slave latches by the rising edge of the
CW_IN master clock divided by 4. For correct operation, a phase relation between Data Ready and the
CW_IN master clock input must be respected (see
Figure 5-2.
The Data Ready duty cycle may vary in accordance with the setup and hold times. The digital data and
Data Ready input rates are equivalent to one fourth of the CW_IN master clock frequency. The Data Ready
rising edge must be (approximately) centered within the digital data input pulse – a minimum setup and
hold time between the data and Data Ready must be observed to ensure enough margin for the input data
time jitter and the different systematic skews amongst the data (trace lengths, package skew, etc.).
Device Pinout
Data or Data Ready (D-CK) Timing
AOUT
D_CK
Data
CS_0 CS_3
C0_T; C9_T
C0_F ; C9_F
A0_T; A9_T
A0_F; A9_F
B0_T; B9_T
B0_F; B9_F
D0_T; D9_T
D0_F; D9_F
CW_IN_T
CW_IN_F
D_CK_T
D_CK_F
Data N
Setup + hold time = 1.2 ns max
2
2
20
20
20
20
4
Data N
Setup time = - 1.3 ns
Hold time = 2.5 ns
VEED
DGND
TS86101G2B
Figure
VEEA
AGND
5-2).
VCCD
Data N+1
Data N+1
DSP_CK_T
DSP_CK_F
DIODE
OUT_T
OUT_F
TS86101G2B
0992D–BDC–04/09
21