TS86101G2BCGL E2V, TS86101G2BCGL Datasheet - Page 30

• Manufacturer Part Number: TS86101G2BCGL
• Manufacturer: E2V

Specifications of TS86101G2BCGL

• Lead Free Status / RoHS Status: Not Compliant

Figure 8-2.
30
CW/2 at TMV Output Delayed
0992D–BDC–04/09
(DSP_CK_T, DSP_CK_F)
(CW_IN_T, CW_IN_F)
(CW_IN_T, CW_IN_F)
CW/2 at TMV Output
CW/4 at TMV Output
(D_CK_T, D_CK_F)
1st Master Latches
2nd Master Latches
Detailed Timing Diagram
3rd Master Latches
CW Master Clock
Port A and Port B
Port C and Port D
1st Slave Latches
Port A and Port B
Port C and Port D
2nd Slave Latches
Data In
Port C and Port D
Port C and Port D
3rd MS DAC Bank
Port A and Port B
Port A and Port B
3rd Slave Latches
4 - 1 MUX Output
CW Resynchro
2 VPP Differential on 100Ω
Port Select D
Port Select A
Port Select B
Port Select C
Data Ready
Note:
1 Vpp Single on 50Ω
(OUT_T, OUT_F)
DAC Bank
DAC Bank
DSP Out
Analog Output
Port A
Port B
Port C
Port D
CW/2
CW/4
Clock
All timing parameters are defined under
TOD Includes Internal Propagation Delay: (Phi4, DAC Core Conversion Time and Package Propagation Delay)
Data Skew
F = 1.2 GHz
Jitter = 300 ps p.p. max
Tdiv4 ~ 2 x Tdiv2
Tdiv2
0
TDSP
Data N - 8
Tdiv2
Delay ~
Tdiv2
Propagation Delay TPD = Pipeline Delay + TOD = 1 Clock Cycle + TOD
1 CW Period
Tsetup
Data N - 7
Jitter = 300 ps p.p. max
Clock Shift
0000
Data N - 6
(15 steps of 200 ps)
Clock Shift Range:
200 ps to 3.1 ns
TCW
Thold
Data N - 5
Tdiv4 ~ 2 x Tdiv2
Tdiv2
Data N - 4
0000
0000
Phi 4
Phi 4
Tdiv2
Delay ~
Tdiv2
Shift Range: 3.1 ns
+ Phi 3
Tdiv 4
1111
Data N - 3
1 CW Period
TPD
Data N - 2
0000
Tconv
“Definitions of Terms” on page
Phi 3
Tmux
1111
1111
1 Pipeline Delay
Shift Range: 3.1 ns
Data N -1
0
Full-scale
1111
Data N + 1
Step
Data N + 2
Data N + 3
35.
%2
%2
Clock
Shift
4
e2v semiconductors SAS 2009
4 x 10
Shift Select
TS86101G2B
Data Ready
DSP Clock Out
Data In
D S P