TS86101G2BCGL E2V, TS86101G2BCGL Datasheet - Page 35

• Manufacturer Part Number: TS86101G2BCGL
• Manufacturer: E2V

Specifications of TS86101G2BCGL

• Lead Free Status / RoHS Status: Not Compliant

10. Definitions of Terms
Table 10-1.
e2v semiconductors SAS 2009
Abbreviation
(ACPR)
(DNL)
(FSR)
(IMD)
(INL)
(NPR)
(SFDR)
(SINAD)
(SNR)
(THD)
TDSP
THold
TPD/TOD
TSetup
(VSWR)
Definitions of Terms
Definition
Adjacent Channel Power Ratio
Differential Non-linearity
Full-scale Range
Inter-modulation Distortion
Integral Non-linearity
Noise Power Ratio
Spurious Free Dynamic Range
Signal-to-Noise and Distortion
Ratio
Signal-to-noise Ratio
Total Harmonic Distortion
Hold Time
Output Propagation Delay
Set-up Time
Voltage Standing Wave Ratio
Description
The ratio in dB between the power in the adjacent channel and the power in the channel
carrying the modulated signal
The maximum deviation in the output step size from the ideal value of one least significant
bit (LSB). A DNL of –1 LSB means that a DAC converter guarantees the transfer function is
monotonic
The maximum difference between the highest and lowest input levels for which various
device performance specifications prevail, unless otherwise noted
The two tones intermodulation (IMD) rejection is the ratio of either output tone to the worst
intermodulation products. The output tone levels are at –6 dB full-scale
The maximum deviation of the output transfer curve at each code from the ideal one after
the gain and offset error are corrected
The NPR is measured to characterize the DAC’s capacity to synthesize a broadband signal.
When using a notch-filtered broadband white-noise DAC input pattern, the Noise Power
Ratio is defined as the ratio of the average out-of-notch to the average in-notch power
spectral density magnitude at the DAC’s output spectrum
The ratio expressed in dB of the RMS signal amplitude to the RMS value of the next highest
spectral component (peak spurious spectral component) measured in the frequency band
DC to Fclk/2. SFDR is the key parameter for selecting a converter to be used in a frequency
domain application. It may be reported in dBc (degrades as signal levels are lowered) or in
dBFS (always full-scale when related back to the converter)
The ratio expressed in dB of the RMS signal amplitude to the RMS sum of all other spectral
components, including the harmonics except DC
The ratio expressed in dB of the RMS signal amplitude to the RMS sum of all other spectral
components excluding the first five harmonics
The ratio expressed in dBc of the RMS sum of the first 10 harmonic components, to the
RMS value of the measured fundamental spectral component
The time delay between the rising edge of the CW_IN master clock and the active DSP clock
rising edge for a clock shift of 0000
The time difference between the rising edge of the differential Data Ready input (zero
crossing) and a point of change of the digital input data (zero crossing of differential input)
The analog output propagation delay. Measured between the rising edge of the differential
CW_IN clock input (zero crossing point) and the zero crossing point of a full-scale analog
output voltage step. TPD corresponds to one CW_IN clock cycle pipeline delay plus an
internal propagation delay (TOD) including package access propagation delays and internal
(on-chip) delays such as clock input buffers and DAC conversion times
The time difference between the point of change of the digital input data (zero crossing of
differential input) and the rising edge of the differential data ready input (zero crossing)
The VSWR corresponds to the DAC output insertion loss due to output power reflection. As
a reminder, a VSWR of 1.12 corresponds to a 20 dB return loss (99% power transmitted and
1% reflected) and therefore to a 0.0436 dB transmission loss
TS86101G2B
0992D–BDC–04/09
35