USB3320C-EZK Standard Microsystems (SMSC), USB3320C-EZK Datasheet - Page 53

• Manufacturer Part Number: USB3320C-EZK
• Description: USB PHY
• Manufacturer: Standard Microsystems (SMSC)

Specifications of USB3320C-EZK

• Lead Free Status / RoHS Status: Compliant

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
Datasheet
SMSC USB3320
6.3.1
(ULPI Register Bit)
linestate[0]
linestate[1]
reserved
int
reserved
SUSPENDM
SIGNAL
DATA[7:0]
NXT
CLK
STP
DIR
on the DP and DM pins to avoid false linestate indications that could result if the pins were allowed to
float.
Entering Low Power/Suspend Mode
To enter Low Power Mode, the Link will write a 0 or clear the SuspendM bit in the
register. After this write is complete, the transceiver will assert DIR high and after a minimum of five
rising edges of CLKOUT, drive the clock low. After the clock is stopped, the transceiver will enter a
low power state to conserve current. Placing the transceiver in Suspend Mode is not related to USB
Suspend. To clarify this point, USB Suspend is initiated when a USB host stops data transmissions
and enters Full-Speed mode with 15KΩ pull-down resistors on DP and DM. The suspended device
goes to Full-Speed mode with a pull-up on DP. Both the host and device remain in this state until one
of them drives DM high (this is called a resume).
While in Low Power Mode, the Data interface is redefined so that the Link can monitor Linestate and
the VBUS voltage. In Low Power Mode DATA[3:0] are redefined as shown in
is the combinational output of the Single-Ended Receivers. The “int” or interrupt signal indicates an
unmasked interrupt has occurred. When an unmasked interrupt or linestate change has occurred, the
Link is notified and can determine if it should wake-up the transceiver.
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[7:4]
MAPS TO
Idle
Figure 6.9 Entering Low Power Mode from Synchronous Mode
T0
Table 6.4 Interface Signal Mapping During Low Power Mode
OUT
OUT
OUT
OUT
OUT
DIRECTION
T1
(reg write)
TXD CMD
T2
DATASHEET
Combinatorial LineState[0] driven directly by the Full-Speed single
ended receiver.
Combinatorial LineState[1] driven directly by the Full-Speed single
ended receiver.
Driven Low
Active high interrupt indication. Must be asserted whenever any
unmasked interrupt occurs.
Driven Low
T3
53
Reg Data[n]
Note 6.2
Note 6.2
T4
Idle
DESCRIPTION
T5
Around
Turn
T6
Table
...
Low Power Mode
Revision 1.0 (07-14-09)
6.4. Linestate[1:0]
Function Control
T10