USB3320C-EZK Standard Microsystems (SMSC), USB3320C-EZK Datasheet - Page 42

• Manufacturer Part Number: USB3320C-EZK
• Description: USB PHY
• Manufacturer: Standard Microsystems (SMSC)

Specifications of USB3320C-EZK

• Lead Free Status / RoHS Status: Compliant

Chapter 6 ULPI Operation
Revision 1.0 (07-14-09)
6.1
STP
RESETB
POR
Data[7:0]
NXT
DIR
The USB3320 uses the industry standard ULPI digital interface to facilitate communication between
the USB Transceiver (PHY) and Link (device controller). The ULPI interface is designed to reduce the
number of pins required to connect a discrete USB Transceiver to an ASIC or digital controller. For
example, a full UTMI+ Level 3 OTG interface requires 54 signals while a ULPI interface requires only
12 signals.
The ULPI interface is documented completely in the “UTMI+ Low Pin Interface (ULPI) Specification
Revision 1.1”. The following sections describe the operating modes of the USB3320 digital interface.
Figure 6.1
USB3320 does not use a “ULPI wrapper” around a UTMI+ PHY core as the ULPI specification implies.
The advantage of a “wrapper less” architecture is that the USB3320 has a lower USB latency than a
design which must first register signals into the PHY’s wrapper before the transfer to the PHY core. A
Overview
ULPI Protocol
Block
illustrates the block diagram of the ULPI digital functions. It should be noted that this
Rx Data
Tx Data
Figure 6.1 ULPI Digital Block Diagram
USB Transmit and Receive Logic
High Speed Data
Full / Low Speed
High Speed TX
Low Speed TX
Full Speed TX
Data Recovery
DATASHEET
Recovery
ULPI Register Array
42
Interrupt Control
HS Tx Data
FS/LS Tx Data
HS RX Data
FS/LS Data
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
Rid State
Machine
Analog
Analog
To RX
To TX
Analog
OTG
To
NOTE:
The ULPI interface
is a wrapperless
design.
To USB
Analog
Audio
SMSC USB3320
Datasheet