AM79C973BKD AMD (ADVANCED MICRO DEVICES), AM79C973BKD Datasheet - Page 39

• Manufacturer Part Number: AM79C973BKD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD

• Lead Free Status / RoHS Status: Compliant

BASIC FUNCTIONS
System Bus Interface
The Am79C973/Am79C975 controllers are designed
to operate as a bus master during normal operations.
S o m e s l ave I/ O a c c e s s e s t o t he A m 7 9C 9 7 3 /
Am79C975 controllers are required in normal opera-
tions as well. Initialization of the Am79C973/
Am79C975 controllers are achieved through a combi-
nation of PCI Configuration Space accesses, bus slave
accesses, bus master accesses, and an optional read
of a ser ial EEPROM that is perfor med by the
Am79C973/Am79C975 controllers. The EEPROM
read operation is performed through the 93C46 EE-
PROM interface. The ISO 8802-3 (IEEE/ANSI 802.3)
Ethernet Address may reside within the serial EE-
PROM. Some Am79C973/Am79C975 controller con-
figuration registers may also be programmed by the
EEPROM read operation.
The Address PROM, on-chip board-configuration reg-
isters, and the Ethernet controller registers occupy 32
bytes of address space. I/O and memory mapped I/O
accesses are supported. Base Address registers in the
PCI configuration space allow locating the address
space on a wide variety of starting addresses.
For diskless stations, the Am79C973/Am79C975 con-
trollers support a ROM or Flash-based (both referred to
as the Expansion ROM throughout this specification)
boot device of up to 1 Mbyte in size. The host can map
the boot device to any memory address that aligns to a
1-Mbyte boundary by modifying the Expansion ROM
Base Address register in the PCI configuration space.
Software Interface
The software interface to the Am79C973/Am79C975
controllers are divided into three parts. One part is the
PCI configuration registers used to identify the
Am79C973/Am79C975 controllers and to setup the
configuration of the device. The setup information in-
cludes the I/O or memory mapped I/O base address,
mapping of the Expansion ROM, and the routing of the
Am79C973/Am79C975 controller interrupt channel.
This allows for a jumperless implementation.
The second portion of the software interface is the di-
rect access to the I/O resources of the Am79C973/
Am79C975 controllers. The Am79C973/Am79C975
controllers occupy 32 bytes of address space that must
begin on a 32-byte block boundary. The address space
can be mapped into I/O or memory space (memory
mapped I/O). The I/O Base Address Register in the
PCI Configuration Space controls the start address of
the address space if it is mapped to I/O space. The
Memory Mapped I/O Base Address Register controls
the start address of the address space if it is mapped
P R E L I M I N A R Y
Am79C973/Am79C975
to memory space. The 32-byte address space is used
by the software to program the Am79C973/Am79C975
controller operating mode, to enable and disable vari-
ous features, to monitor operating status, and to re-
quest particular functions to be executed by the
Am79C973/Am79C975 controllers.
The third portion of the software interface is the de-
scriptor and buffer areas that are shared between the
software and the Am79C973/Am79C975 controllers
during normal network operations. The descriptor area
boundaries are set by the software and do not change
during normal network operations. There is one de-
scriptor area for receive activity and there is a separate
area for transmit activity. The descriptor space contains
relocatable pointers to the network frame data, and it is
used to transfer frame status from the Am79C973/
Am79C975 controllers to the software. The buffer
areas are locations that hold frame data for transmis-
sion or that accept frame data that has been received.
Network Interfaces
The Am79C973/Am79C975 controllers provide all of
the PHY layer functions for 10 Mbps (10BASE-T) or
100 Mbps (100BASE-TX). It also provides a Pseudo
ECL (PECL) interface for 100BASE-FX fiber networks.
The Am79C973/Am79C975 controllers support both
half-duplex and full-duplex operation on network inter-
faces.
Serial Management Interface
(Am79C975)
The Am79C975 controller provides a 3-pin interface
based on the I
system to monitor the status of the system hardware
and report the results to the management station or
system administrator. Monitored information may in-
clude critical system parameters, such as voltage, tem-
p e r a t u r e, a n d fa n s p e e d , a s w e l l a s s y s t e m
management events, such as chassis intrusion, operat-
ing system errors and power-on failures.
MII Interface
The Am79C973/Am79C975 supports an MII interface
m o d e t h a t m a ke s t h e d ev i c e o p e r a t e l i k e a
PCnet-FAST+ device. The MII pins are multiplexed with
the expansion bus pins, which means the device will
only support either an EPROM/Flash or an external
PHY but not both. To enter this mode, set PHYSELEN
(BCR2, bit 13) = 1 and PHYSEL (BCR18, bit 4 and
bit 3) = 10. This mode isolates the internal PHY to allow
interface with an external PHY. For a more detailed de-
scription of the MII interface including timing diagrams
see Appendix C. Refer to the connection diagram to
see how the pins are multiplexed.
2
C and SMBus standards that enables a
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