AM79C973BKD AMD (ADVANCED MICRO DEVICES), AM79C973BKD Datasheet - Page 181

• Manufacturer Part Number: AM79C973BKD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD

• Lead Free Status / RoHS Status: Compliant

31-8
7-0
BCR26: SRAM Boundary Register
Bit
Note: Bits 7-0 in this register are programmable
through the EEPROM.
31-8
7-0
SRAM_BND SRAM Boundary. Specifies the
SRAM_SIZE SRAM Size. Specifies the upper
RES
RES
Name
upper 8 bits of the 16-bit address
boundary where the receive buffer
Reserved locations. Written as
zeros and read as undefined.
8 bits of the 16-bit total size of the
SRAM
SRAM_SIZE accounts for a 512-
byte page. The starting address
for the lower 8 bits is assumed to
be 00h and the ending address
for the lower is assumed to be
FFh. Therefore, the maximum ad-
dress range is the starting ad-
dress of 0000h to ending address
of ((SRAM_SIZE +1) * 256
words)
SRAM_SIZE value of all zeros
specifies that no SRAM will be
used and the internal FIFOs will
be joined into a contiguous FIFO
similar to the PCnet-PCI II con-
troller.
Reserved locations. Written as
zeros and read as undefined.
Note: The minimum allowed
number of pages is eight for nor-
mal
Am79C973/Am79C975 controller
will not operate correctly with less
than the eight pages of memory.
When the minimum number of
pages is used, these pages must
be allocated four each for trans-
mit and receive.
CAUTION:
SRAM_BND and SRAM_SIZE
to the same value will cause
data corruption except in the
case where SRAM_SIZE is 0.
Read accessible always; write
accessible only when the STOP
bit is set. SRAM_SIZE is set to
000000b during H_RESET and is
unaffected
STOP.
Description
network
buffer.
or
by
operation.
S_RESET
Each
17FFh.
Programming
P R E L I M I N A R Y
Am79C973/Am79C975
bit
The
An
or
in
BCR27: SRAM Interface Control Register
Bit
31-16 RES
15
Maximum SRAM_BND Address
Minimum SRAM_BND
PTR TST
SRAM Addresses
Table 34. SRAM_BND Programming
Name
Address
begins in the SRAM. The transmit
buffer in the SRAM begins at ad-
dress 0 and ends at the address
located just before the address
specified by SRAM_BND. There-
fore, the receive buffer always be-
gins on a 512 byte boundary. The
lower bits are assumed to be ze-
ros. SRAM_BND has no effect in
the Low Latency Receive mode.
Note: The minimum allowed
number of pages is four. The
Am79C973/Am79C975 controller
will not operate correctly with less
than four pages of memory per
queue.
SRAM_BND programming de-
tails.
CAUTION:
SRAM_BND and SRAM_SIZE
to the same value will cause
data corruption except in the
case where SRAM SIZE is 0.
Read accessible always; write
accessible only when the STOP
bit is set. SRAM_BND is set to
00000000b
and is unaffected by S_RESET or
STOP.
Reserved locations. Written as
zeros and read as undefined.
Reserved. Reserved for manu-
facturing tests. Written as zero
and read as undefined.
Note: Use of this bit will cause
data corruption and erroneous
operation.
Read/Write accessible always.
PTR_TST
H_RESET and is unaffected by
S_RESET and the STOP bit.
Description
See
is
during
SRAM_BND [7:0]
Table
set
Programming
04h
13h
to
H_RESET
34
0
181
for
by