AM79C973BKD AMD (ADVANCED MICRO DEVICES), AM79C973BKD Datasheet - Page 108

• Manufacturer Part Number: AM79C973BKD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD

• Lead Free Status / RoHS Status: Compliant

STOP terminates all network activity abruptly. The host
can use the suspend mode (SPND, CSR5, bit 0) to ter-
minate all network activity in an orderly sequence be-
fore setting the STOP bit.
Power on Reset
Power on Reset (POR) is generated when the
Am79C973/Am79C975 controller is powered up. POR
generates a hardware reset (H_RESET). In addition, it
clears some bits that H_RESET does not affect.
Software Access
PCI Configuration Registers
The Am79C973/Am79C975 controller implements the
256-byte configuration space as defined by the PCI
108
31
Base-Class
DATA_REG
MAX_LAT
Reserved
24
Subsystem ID
Device ID
Status
PMC
23
PMCSR_BSE
Header Type
Sub-Class
MIN_GNT
Reserved
Memory Mapped I/O Base Address
Expansion ROM Base Address
Table 19. PCI Configuration Space Layout
Cardbus CIS Pointer
I/O Base Address
16
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
P R E L I M I N A R Y
Am79C973/Am79C975
15
Programming IF
NXT_ITM_PTR
Latency Timer
Interrupt Pin
specification revision 2.1. The 64-byte header includes
all registers required to identify the Am79C973/
Am79C975 controller and its function. Additionally, PCI
Power Management Interface registers are imple-
mented at location 40h - 47h. The layout of the
Am79C973/Am79C975 PCI configuration space is
shown in Table 19.
The PCI configuration registers are accessible only by
configuration cycles. All multi-byte numeric fields follow
little endian byte ordering. All write accesses to Re-
served locations have no effect; reads from these loca-
tions will return a data value of 0.
Subsystem Vendor ID
8
Command
Vendor ID
PMCSR
7
Interrupt Line
Revision ID
CAP-PTR
Reserved
CAP_ID
0
Offset
0Ch
1Ch
2Ch
3Ch
44H
FCh
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
38h
40h
.
.