AM79C973BKD AMD (ADVANCED MICRO DEVICES), AM79C973BKD Datasheet - Page 129

• Manufacturer Part Number: AM79C973BKD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD

• Lead Free Status / RoHS Status: Compliant

1-0
CSR4: Test and Features Control
Certain bits in CSR4 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR4 and write back
the value just read to clear the interrupt condition.
Bit
31-16
15
RES
Name
RES
RES
Byte swap only affects data
transfers that involve the FIFOs.
Initialization block transfers are
not affected by the setting of the
BSWP bit. Descriptor transfers
are not affected by the setting of
the BSWP bit. RDP, RAP, BDP
and PCI configuration space ac-
cesses are not affected by the
setting of the BSWP bit. Address
PROM transfers are not affected
by the setting of the BSWP bit.
Expansion ROM accesses are
not affected by the setting of the
BSWP bit.
Note that the byte ordering of the
PCI bus is defined to be little En-
dian. BSWP should not be set to
1
Am79C975 controller is used in a
PCI bus application.
Read/Write accessible always.
BSWP is cleared by H_RESET or
S_RESET and is not affected by
STOP.
value of this bit is a 0. Writing a 1
to this bit has no effect on device
function. If a 1 is written to this bit,
then a 1 will be read back. Exist-
ing drivers may write a 1 to this bit
for compatibility, but new drivers
should write a 0 to this bit and
should treat the read value as un-
defined.
zeros and read as undefined.
legacy software to write a 1 to this
location. This bit must be set
back to 0 before setting INIT or
STRT bits.
Read/Write accessible always.
This bit is cleared by H_RESET
Reserved location. The default
Description
Reserved locations. Written as
Reserved location. It is OK for
when
the
Am79C973/
P R E L I M I N A R Y
Am79C973/Am79C975
14
13
12
11
10
ASTRP_RCV Auto Strip Receive. When set,
APAD_XMT Auto Pad Transmit. When set,
DMAPLUS Writing and reading from this bit
RES
TXDPOLL
or S_RESET and is unaffected by
the STOP bit.
Read/Write accessible always.
TXDPOLL
H_RESET or S_RESET and is
unaffected by the STOP bit.
Read/Write accessible always.
APAD_XMT
H_RESET or S_RESET and is
unaffected by the STOP bit.
Read/Write accessible always.
ASTRP_RCV
H_RESET or S_RESET and is
unaffected by the STOP bit.
has no effect. DMAPLUS is al-
ways set to 1.
Reserved Location. Written as
zero and read as undefined.
Disable Transmit Polling. If TXD-
POLL is set, the Buffer Manage-
ment Unit will disable transmit
polling. Likewise, if TXDPOLL is
cleared, automatic transmit poll-
ing is enabled. If TXDPOLL is set,
TDMD bit in CSR0 must be set in
order to initiate a manual poll of a
transmit descriptor. Transmit de-
scriptor polling will not take place
if TXON is reset. Transmit polling
will take place following Receive
activities.
APAD_XMT enables the auto-
matic padding feature. Transmit
frames will be padded to extend
them to 64 bytes including FCS.
The FCS is calculated for the en-
tire frame, including pad, and ap-
pended after the pad field.
APAD_XMT will override the pro-
gramming of the DXMTFCS bit
(CSR15, bit 3) and of the
ADD_FCS bit (TMD1, bit 29) for
frames shorter than 64 bytes.
ASTRP_RCV enables the auto-
matic pad stripping feature. The
pad and FCS fields will be
stripped from receive frames and
not placed in the FIFO.
is
is
is
cleared
cleared
cleared
129
by
by
by