AM79C973BKD AMD (ADVANCED MICRO DEVICES), AM79C973BKD Datasheet - Page 110

• Manufacturer Part Number: AM79C973BKD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD

• Lead Free Status / RoHS Status: Compliant

All I/O resources must be accessed in word quantities
and on word addresses. The Address PROM locations
can also be read in byte quantities. The only allowed
DWord operation is a write access to the RDP, which
switches the device to DWord I/O mode. A read access
other than listed in the table below will yield undefined
data, a write operation may cause unexpected repro-
gramming of the Am79C973/Am79C975 control regis-
ters. Table 21 shows legal I/O accesses in Word I/O
mode.
Double Word I/O Mode
The Am79C973/Am79C975 controller can be config-
ured to operate in DWord (32-bit) I/O mode. The soft-
110
00h - 0Fh
18h - 1Fh
Table 20. I/O Map In Word I/O Mode (DWIO = 0)
Offset
10h
12h
14h
16h
No. of
Bytes
16
2
2
2
2
8
RAP (shared by RDP and BDP)
Reset Register
Reserved
Register
APROM
RDP
BDP
P R E L I M I N A R Y
Am79C973/Am79C975
ware can invoke the DWIO mode by performing a
DWord write access to the I/O location at offset 10h
(RDP). The data of the write access must be such that
it does not affect the intended operation of the
Am79C973/Am79C975 controller. Setting the device
into 32-bit I/O mode is usually the first operation after
H_RESET or S_RESET. The RAP register will point to
CSR0 at that time. Writing a value of 0 to CSR0 is a
safe operation. DWIO (BCR18, bit 7) will be set to 1 as
an indication that the Am79C973/Am79C975 controller
operates in 32-bit I/O mode.
Note: Even though the I/O resource mapping changes
when the I/O mode setting changes, the RDP location
offset is the same for both modes. Once the DWIO bit
has been set to 1, only H_RESET can clear it to 0. The
DWIO mode setting is unaffected by S_RESET or set-
ting of the STOP bit. Table 22 shows how the 32 bytes
of address space are used in DWord I/O mode.
All I/O resources must be accessed in DWord quanti-
ties and on DWord addresses. A read access other
than listed in Table 23 will yield undefined data, a write
operation may cause unexpected reprogramming of
the Am79C973/Am79C975 control registers.