PIC18F65K22-E/PT Microchip Technology, PIC18F65K22-E/PT Datasheet - Page 186

• Manufacturer Part Number: PIC18F65K22-E/PT
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, GP 64 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K22-E/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
TABLE 12-15: PORTH FUNCTIONS (CONTINUED)
DS39960D-page 186
RH4/CCP9/
P3C/AN12/
C2INC
RH5/CCP8/
P3B/AN13/
C2IND
RH6/CCP7/
P1C/AN14/
C1INC
RH7/CCP6/
P1B/AN15
Legend:
Pin Name
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Function
C2INC
C2IND
C1INC
CCP9
CCP8
CCP7
CCP6
AN12
AN13
AN14
AN15
RH4
RH5
RH6
RH7
P3C
P3B
P1C
P1B
Setting
TRIS
0
1
0
1
0
1
x
0
1
0
1
0
1
x
0
1
0
1
0
1
x
0
1
0
1
0
1
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
ANA
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
—
—
—
—
LATH<4> data output.
PORTH<4> data input.
CCP9 compare/PWM output; takes priority over port data.
CCP9 capture input.
ECCP3 PWM Output C.
May be configured for tri-state during Enhanced PWM.
A/D Input Channel 12.
Default input configuration on POR; does not affect digital input.
Comparator 2 Input C.
LATH<5> data output.
PORTH<5> data input.
CCP8 compare/PWM output; takes priority over port data.
CCP8 capture input.
ECCP3 PWM Output B.
May be configured for tri-state during Enhanced PWM.
A/D Input Channel 13.
Default input configuration on POR; does not affect digital input.
Comparator 2 Input D.
LATH<6> data output.
PORTH<6> data input.
CCP7 compare/PWM output; takes priority over port data.
CCP7 capture input.
ECCP1 PWM Output C.
May be configured for tri-state during Enhanced PWM.
A/D Input Channel 14.
Default input configuration on POR; does not affect digital input.
Comparator 1 Input C.
LATH<7> data output.
PORTH<7> data input.
CCP6 compare/PWM output; takes priority over port data.
CCP6 capture input.
ECCP1 PWM Output B.
May be configured for tri-state during Enhanced PWM.
A/D Input Channel 15.
Default input configuration on POR; does not affect digital input.
Description
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