PIC18F65K22-E/PT Microchip Technology, PIC18F65K22-E/PT Datasheet - Page 185

• Manufacturer Part Number: PIC18F65K22-E/PT
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, GP 64 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K22-E/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.9
PORTH is an 8-bit wide, bidirectional I/O port. The
corresponding Data Direction and Output Latch registers
are TRISH and LATH.
All pins on PORTH are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
TABLE 12-15: PORTH FUNCTIONS
 2009-2011 Microchip Technology Inc.
RH0/AN23/A16
RH1/AN22/A17
RH2/AN21/A18
RH3/AN20/A19
Legend:
Note:
Pin Name
PORTH, LATH and
TRISH Registers
PORTH is available only on the 80-pin
devices.
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Function
AN23
AN22
AN21
AN20
RH0
RH1
RH2
RH3
A16
A17
A18
A19
Setting
TRIS
0
1
1
x
0
1
1
x
0
1
1
x
0
1
1
x
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
LATH<0> data output.
PORTH<0> data input.
A/D Input Channel 23.
Default input configuration on POR; does not affect digital input.
External memory interface, Address Line 16; takes priority over port
data.
LATH<1> data output.
PORTH<1> data input.
A/D Input Channel 22.
Default input configuration on POR; does not affect digital input.
External memory interface, Address Line 17; takes priority over port
data.
LATH<2> data output.
PORTH<2> data input.
A/D Input Channel 21.
Default input configuration on POR; does not affect digital input.
External memory interface, Address Line 18; takes priority over port
data.
LATH<3> data output.
PORTH<3> data input.
A/D Input Channel 20.
Default input configuration on POR; does not affect digital input.
External memory interface, Address Line 19; takes priority over port
data.
PIC18F87K22 FAMILY
EXAMPLE 12-8:
BANKSEL ANCON2
MOVLW
MOVWF
MOVLW
MOVWF
BANKSEL TRISH
MOVLW
MOVWF
CLRF
CLRF
0Fh
ANCON2
0Fh
ANCON1
0CFh
TRISH
PORTH
LATH
Description
; Select bank with ANCON2 register
; Configure PORTH as
; digital I/O
; Configure PORTH as
; digital I/O
; Select bank with TRISH register
; Value used to
; Set RH3:RH0 as inputs
; initialize data
; direction
; RH5:RH4 as outputs
; RH7:RH6 as inputs
; Initialize PORTH by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
INITIALIZING PORTH
DS39960D-page 185