PIC18F65K22-E/PT Microchip Technology, PIC18F65K22-E/PT Datasheet - Page 183

• Manufacturer Part Number: PIC18F65K22-E/PT
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, GP 64 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K22-E/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.8
PORTG is a 5-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISG and LATG.
PORTG is multiplexed with the AUSART and CCP,
ECCP, Analog, Comparator, RTCC and Timer input
functions
PORTG pins have Schmitt Trigger input buffers. The
open-drain functionality for the CCPx and UART can be
configured using ODCONx.
TABLE 12-13: PORTG FUNCTIONS
 2009-2011 Microchip Technology Inc.
RG0/ECCP3/
P3A
RG1/TX2/CK2/
AN19/C3OUT
Legend:
Pin Name
PORTG, TRISG and
LATG Registers
(Table
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
12-13). When operating as I/O, all
Function
ECCP3
C3OUT
AN19
RG0
RG1
P3A
TX2
CK2
Setting
TRIS
0
1
0
1
0
0
1
1
1
1
1
x
I/O
O
O
O
O
O
O
O
I
I
I
I
I
Type
ANA
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
—
LATG<0> data output.
PORTG<0> data input.
ECCP3 compare output and ECCP3 PWM output; takes priority over
port data.
ECCP3 capture input.
ECCP3 PWM Output A.
May be configured for tri-state during Enhanced PWM shutdown
events.
LATG<1> data output.
PORTG<1> data input.
Synchronous serial data output (EUSART module); takes priority over
port data.
Synchronous serial data input (EUSART module); user must configure
as an input.
Synchronous serial clock input (EUSART module).
A/D Input Channel 19.
Default input configuration on POR. Does not affect digital output.
Comparator 3 output.
PIC18F87K22 FAMILY
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS bit
settings. The pin override value is not loaded into the
TRIS register. This allows read-modify-write of the TRIS
register without concern due to peripheral overrides.
EXAMPLE 12-7:
CLRF
BCF
CLRF
BANKSEL ANCON2
MOVLW
MOVWF
BANKSEL TRISG
MOVLW
MOVWF
PORTG
CM1CON, CON ; disable
LATG
0F0h
ANCON2
04h
TRISG
Description
; Initialize PORTG by
; clearing output
; data latches
; comparator 1
; Alternate method
; to clear output
; data latches
; Select bank with ACON2 register
; make AN16 to AN19
; digital
; Select bank with TRISG register
; Value used to
; initialize data
; direction
; Set RG1:RG0 as
; outputs
; RG2 as input
; RG4:RG3 as inputs
INITIALIZING PORTG
DS39960D-page 183