PIC18F65K22-E/PT Microchip Technology, PIC18F65K22-E/PT Datasheet - Page 123

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PIC18F65K22-E/PT

Manufacturer Part Number
PIC18F65K22-E/PT
Description
32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, GP 64 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet

Specifications of PIC18F65K22-E/PT

Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F65K22-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
8.2
The PIC18F87K22 family of devices can be indepen-
dently configured for different address and data widths
on the same memory bus. Both address and data width
are set by Configuration bits in the CONFIG3L register.
As Configuration bits, this means that these options
can only be configured by programming the device and
are not controllable in software.
The BW bit selects an 8-bit or 16-bit data bus width.
Setting this bit (default) selects a data width of 16 bits.
The ABW<1:0> bits determine both the program mem-
ory operating mode and the address bus width. The
available options are 20-bit, 16-bit and 12-bit, as well
as Microcontroller mode (external bus is disabled).
Selecting a 16-bit or 12-bit width makes a correspond-
ing number of high-order lines available for I/O
functions. These pins are no longer affected by the
setting of the EBDIS bit. For example, selecting a
16-Bit Addressing mode (ABW<1:0> = 01) disables
A<19:16> and allows PORTH<3:0> to function without
interruptions from the bus. Using the smaller address
widths allows users to tailor the memory bus to the size
of the external memory space for a particular design
while freeing up pins for dedicated I/O operation.
Because the ABW bits have the effect of disabling pins
for memory bus operations, it is important to always
select an address width at least equal to the data width.
If a 12-bit address width is used with a 16-bit data
width, the upper four bits of data will not be available on
the bus.
All combinations of address and data widths require
multiplexing of address and data information on the
same lines. The address and data multiplexing, as well
as I/O ports made available by the use of smaller
address widths, are summarized in
TABLE 8-2:
 2009-2011 Microchip Technology Inc.
Data Width
16-bit
8-bit
Address and Data Width
ADDRESS AND DATA LINES FOR DIFFERENT ADDRESS AND DATA WIDTHS
Address Width
12-bit
16-bit
20-bit
16-bit
20-bit
Table
8-2.
Corresponding Ports)
Multiplexed Data and
Address Lines (and
(PORTD<7:0>)
(PORTD<7:0>,
PORTE<7:0>)
AD<15:0>
AD<7:0>
PIC18F87K22 FAMILY
8.2.1
By default, the address presented on the external bus
is the value of the PC. In practical terms, this means
that addresses in the external memory device, below
the top of on-chip memory, are unavailable to the
microcontroller. To access these physical locations, the
glue logic between the microcontroller and the external
memory must somehow translate addresses.
To simplify the interface, the external bus offers an
extension of Extended Microcontroller mode that
automatically performs address shifting. This feature is
controlled by the EASHFT Configuration bit. Setting
this bit offsets addresses on the bus by the size of the
microcontroller’s on-chip program memory and sets
the bottom address at 0000h. This allows the device to
use the entire range of physical addresses of the
external memory.
8.2.2
As an extension of 20-bit address width operation, the
External Memory Bus can also fully address a 2-Mbyte
memory space. This is done by using the Bus Address
Bit 0 (BA0) control line as the Least Significant bit of the
address. The UB and LB control signals may also be
used with certain memory devices to select the upper
and lower bytes within a 16-bit wide data word.
This addressing mode is available in both 8-Bit and
certain 16-Bit Data Width modes. Additional details are
provided in
and
Section 8.7 “8-Bit Data Width
(and Corresponding
Address Only Lines
A<19:16>, AD<15:8>
(PORTE<3:0>)
(PORTE<7:0>)
(PORTH<3:0>,
(PORTH<3:0>)
PORTE<7:0>)
ADDRESS SHIFTING ON THE
EXTERNAL BUS
21-BIT ADDRESSING
Section 8.6.3 “16-Bit Byte Select Mode”
AD<15:8>
AD<11:8>
A<19:16>
Ports)
Ports Available
DS39960D-page 123
PORTE<7:4>,
Mode”.
All of PORTH
All of PORTH
All of PORTH
for I/O

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