DJLXT971ALE.A4 Cortina Systems Inc, DJLXT971ALE.A4 Datasheet - Page 89

• Manufacturer Part Number: DJLXT971ALE.A4
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT971ALE.A4

• Lead Free Status / RoHS Status: Not Compliant

LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
Table 58
Table 59
Cortina Systems
Interrupt Enable Register - Address 18, Hex 12
Status Change Register - Address 19, Hex 13 (Sheet 1 of 2)
®
18.
15:9
18.8
18.7
18.6
18.5
18.4
18.3
18.2
18.1
18.0
1. R/W = Read /Write
19.15:9
19.8
19.7
19.6
19.5
1. R/W = Read/Write, RO = Read Only, SC = Self Clearing.
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Bit
Bit
Reserved
Reserved
ANMSK
SPEEDMSK
DUPLEXMSK
LINKMSK
Reserved
Reserved
INTEN
TINT
Reserved
Reserved
ANDONE
SPEEDCHG
DUPLEXCHG
Name
Name
Ignore on Read.
Ignore on Read.
Auto-negotiation Status
0 = Auto-negotiation has not completed.
1 = Auto-negotiation has completed.
Speed Change Status
0 = A Speed Change has not occurred since last
1 = A Speed Change has occurred since last reading
Duplex Change Status
0 = A Duplex Change has not occurred since last
1 = A Duplex Change has occurred since last
Write as ‘0’. Ignore on Read.
Write as ‘0’. Ignore on Read.
Mask for Auto Negotiate Complete
0 = Do not allow event to cause interrupt.
1 = Enable event to cause interrupt.
Mask for Speed Interrupt
0 = Do not allow event to cause interrupt.
1 = Enable event to cause interrupt.
Mask for Duplex Interrupt
0 = Do not allow event to cause interrupt.
1 = Enable event to cause interrupt.
Mask for Link Status Interrupt
0 = Do not allow event to cause interrupt.
1 = Enable event to cause interrupt.
Write as ‘0’. Ignore on Read.
Write as ‘0’. Ignore on Read.
Interrupt Enable.
0 = Disable interrupts.
1 = Enable interrupts.
Test Force Interrupt
0 = Normal operation.
1 = Force interrupt on MDINT_L
reading this register.
this register.
reading this register.
reading this register.
Description
Description
Product-Specific Registers
9.0 Register Definitions -
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO/
RO/
RO/
RO
RO
SC
SC
SC
1
1
Default
Default
N/A
Page 89
N/A
N/A
0
0
0
0
0
0
0
0
0
0
0
0