DJLXT971ALE.A4 Cortina Systems Inc, DJLXT971ALE.A4 Datasheet - Page 41

• Manufacturer Part Number: DJLXT971ALE.A4
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT971ALE.A4

• Lead Free Status / RoHS Status: Not Compliant

LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
Figure 13
5.6.7.1
5.6.7.2
Note:
Cortina Systems
Loopback Paths
Operational Loopback
Internal Digital Loopback (Test Loopback)
A test loopback function is provided for diagnostic testing of the LXT971A PHY. During
test loopback, twisted-pair and fiber interfaces are disabled. Data transmitted by the MAC
is internally looped back by the LXT971A PHY and returned to the MAC.
Test loopback is available for both 100BASE-TX and 10BASE-T operation, and is enabled
by setting the following register bits:
Test loopback is also available for 100BASE-FX operation. Test loopback in this mode is
enabled by setting register bit 0.14 = 1 and tying the SD input to an LVPECL logic High
value (2.4 V).
Parallel detection can resolve the PHY configuration.
®
• Operational loopback is provided for 10 Mbps half-duplex links when register bit 16.8
• Operational loopback is not provided for 100 Mbps links, full-duplex links, or when
• register bit 0.14 = 1 (Setting to enable loopback mode)
• register bit 0.8 = 1 (Setting for full-duplex mode)
• register bit 0.12 = 0 (Disable auto-negotiation)
LXT971A Single-Port 10/100 Mbps PHY Transceiver
= 0. Data that the MAC (TXData) transmits loops back on the receive side of the MII
(RXData).
Register 16.8 = 1.
MII
LXT97x PHY
Loopback
Operational
Loopback
10T
Digital
Block
Test Loopback
Loopback
100X
Analog
Block
5.6 MII Operation
Driver
Driver
FX
TX
B3392-02
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