DJLXT971ALE.A4 Cortina Systems Inc, DJLXT971ALE.A4 Datasheet - Page 19

• Manufacturer Part Number: DJLXT971ALE.A4
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT971ALE.A4

• Lead Free Status / RoHS Status: Not Compliant

LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
Table 6
Cortina Systems
MII Controller Interface Signal Descriptions
®
PBGA
Pin#
LXT971A Single-Port 10/100 Mbps PHY Transceiver
D3
E7
D8
A1
LQFP
Pin#
43
42
64
3
MDINT_L
Symbol
MDDIS
MDIO
MDC
Type
OD
I/O
I
I
Management Data Disable.
When MDDIS is High, the MDIO is disabled from read and write
operations.
When MDDIS is Low at power-up or reset, the Hardware Control
Interface pins control only the initial or “default” values of their
respective register bits.
After the power-up/reset cycle is complete, bit control reverts to the
MDIO serial channel.
Management Data Clock.
Clock for the MDIO serial data channel.
Maximum frequency is 8 MHz.
Management Data Input/Output.
Bidirectional serial data channel for PHY/STA communication.
Management Data Interrupt.
When register bit 18.1 = 1, an active Low output on this pin
indicates status change.
Interrupt is cleared by reading Register 19.
Signal Description
4.0 Signal Descriptions
Page 19