DJLXT971ALE.A4 Cortina Systems Inc, DJLXT971ALE.A4 Datasheet - Page 28

• Manufacturer Part Number: DJLXT971ALE.A4
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT971ALE.A4

• Lead Free Status / RoHS Status: Not Compliant

LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
5.2.3.1.1
5.2.3.1.2
Figure 4
Figure 5
5.2.3.1.3
Cortina Systems
The LXT971A PHY supports the IEEE 802.3 MII Management Interface also known as the
Management Data Input/Output (MDIO) Interface. This interface allows upper-layer
devices to monitor and control the state of the LXT971A PHY. The MDIO interface
consists of a physical connection, a specific protocol that runs across the connection, and
an internal set of addressable registers.
Some registers are required and their functions are defined by the IEEE 802.3 standard.
The LXT971A PHY also supports additional registers for expanded functionality. The
LXT971A PHY supports multiple internal registers, each of which is 16 bits wide. Specific
register bits are referenced using an “X.Y” notation, where X is the register number (0-31)
and Y is the bit number (0-15).
The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of
this interface is controlled by the MDDIS input pin. When MDDIS is High, the MDIO read
and write operations are disabled and the Hardware Control Interface provides primary
configuration control. When MDDIS is Low, the MDIO port is enabled for both read and
write operations and the Hardware Control Interface is not used.
MDIO Addressing
The MDIO addressing protocol allows a controller to communicate with multiple PHYs.
Pins ADDR[4:0] can be used to determine the PHY device address that is selected.
MDIO Frame Structure
The physical interface consists of a data line (MDIO) and clock line (MDC). The frame
structure is shown in
MDIO Interface timing is given in
Management Interface Read Frame Structure
Management Interface Write Frame Structure
MII Interrupts
Figure 6 shows the MII interrupt logic.
pin (MDINT_L) and two dedicated interrupt registers, Register 18 and Register 19.
®
MDIO
(Read)
(Write)
MDC
LXT971A Single-Port 10/100 Mbps PHY Transceiver
MDIO
MDC
High Z
Idle
Preamble
32 "1"s
Preamble
32 "1"s
0
0
ST
ST
1
1
Figure 4
1
0
Op Code
Op Code
1
0
Write
and
A4
A4
PHY Address
PHY Address
Section 7.0, Electrical Specifications.
Figure 5
A3
A3
The LXT971A PHY provides a hardware interrupt
A0
A0
Write
R4
R4
(Read and Write).
Register Address
Register Address
R3
R3
R0
R0
1
Z
Around
Around
Turn
Turn
0
0
D15
D15
5.2 Network Media / Protocol
D15
D14
D14
Data
Read
D14
Data
D1
D1
D1
D0
D0
B3490-01
Idle
Idle
B3489-01
Support
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