DJLXT971ALE.A4 Cortina Systems Inc, DJLXT971ALE.A4 Datasheet - Page 39

• Manufacturer Part Number: DJLXT971ALE.A4
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT971ALE.A4

• Lead Free Status / RoHS Status: Not Compliant

LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
Figure 12
5.6.2
5.6.3
5.6.4
Cortina Systems
Clocking for Link Down Clock Transition
Transmit Enable
The MAC must assert TX_EN the same time as the first nibble of preamble and de-assert
TX_EN after the last nibble of the packet.
Receive Data Valid
The LXT971A PHY asserts RX_DV when it receives a valid packet. Timing changes
depend on line operating speed:
Carrier Sense
Carrier Sense (CRS) is an asynchronous output.
Table 14
collision signals. Carrier sense is not generated when a packet is transmitted and in full-
duplex mode.
®
• For 100BASE-TX links, RX_DV is asserted from the first nibble of preamble to the last
• For 10BASE-T links, the entire preamble is truncated. RX_DV is asserted with the first
• CRS is always generated when the LXT971A PHY receives a packet from the line.
• CRS is also generated when the LXT971A PHY is in half-duplex mode when a packet
LXT971A Single-Port 10/100 Mbps PHY Transceiver
nibble of the data packet.
nibble of the Start of Frame Delimiter (SFD) “5D” and remains asserted until the end
of the packet.
is transmitted.
summarizes the conditions for assertion of carrier sense, data loopback, and
RX_CLK
TX_CLK
Clock
Any
Clock transition time does not exceed
2X the nominal clock period:
10 Mbps = 2.5 MHz
100 Mbps = 25 MHz
Link-Down Condition/Auto-Negotiate Enabled
2.5 MHz
Clock
B3503-01
5.6 MII Operation
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